📄 io_map.h
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/** ###################################################################
** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
** Filename : IO_Map.H
** Project : LowFreqSG
** Processor : MC68HC908LV8CFA
** Beantype : IO_Map
** Version : Driver 01.09
** Compiler : CodeWarrior HC08 C Compiler
** Date/Time : 2006-9-5, 17:47
** Abstract :
** IO_Map.h - implements an IO device's mapping.
** This module contains symbol definitions of all peripheral
** registers and bits.
** Settings :
**
** Contents :
** No public methods
**
** (c) Copyright UNIS, spol. s r.o. 1997-2006
** UNIS, spol. s r.o.
** Jundrovska 33
** 624 00 Brno
** Czech Republic
** http : www.processorexpert.com
** mail : info@processorexpert.com
** ###################################################################*/
#ifndef _IO_MAP_H
#define _IO_MAP_H
/* Based on CPU DB MC68HC908LV8_52, version 2.89.060 (RegistersPrg V2.05) */
/* DataSheet : MC68HC908LV8 Rev. 2 12/2005 */
#include "PE_Types.h"
#pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */
/*********************************************/
/* */
/* PE I/O map */
/* */
/*********************************************/
/**************** interrupt vector table ****************/
#define INT_ADC 0x0000FFDA
#define INT_KBD 0x0000FFDC
#define Reserved2 0x0000FFDE
#define Reserved3 0x0000FFE0
#define Reserved4 0x0000FFE2
#define Reserved5 0x0000FFE4
#define Reserved6 0x0000FFE6
#define Reserved7 0x0000FFE8
#define INT_TIM2Ovr 0x0000FFEA
#define INT_TIM2CH1 0x0000FFEC
#define INT_TIM2CH0 0x0000FFEE
#define INT_TIM1Ovr 0x0000FFF0
#define INT_TIM1CH1 0x0000FFF2
#define INT_TIM1CH0 0x0000FFF4
#define INT_PLL 0x0000FFF6
#define INT_LVI 0x0000FFF8
#define INT_IRQ 0x0000FFFA
#define INT_SWI 0x0000FFFC
#define INT_RESET 0x0000FFFE
/**************** registers I/O map ****************/
/*** PTA - Port A Data Register; 0x00000000 ***/
typedef union {
byte Byte;
struct {
byte PTA0 :1; /* Port A Data Bit 0 */
byte PTA1 :1; /* Port A Data Bit 1 */
byte PTA2 :1; /* Port A Data Bit 2 */
byte PTA3 :1; /* Port A Data Bit 3 */
byte PTA4 :1; /* Port A Data Bit 4 */
byte PTA5 :1; /* Port A Data Bit 5 */
byte PTA6 :1; /* Port A Data Bit 6 */
byte PTA7 :1; /* Port A Data Bit 7 */
} Bits;
} PTASTR;
extern volatile PTASTR _PTA @0x00000000;
#define PTA _PTA.Byte
#define PTA_PTA0 _PTA.Bits.PTA0
#define PTA_PTA1 _PTA.Bits.PTA1
#define PTA_PTA2 _PTA.Bits.PTA2
#define PTA_PTA3 _PTA.Bits.PTA3
#define PTA_PTA4 _PTA.Bits.PTA4
#define PTA_PTA5 _PTA.Bits.PTA5
#define PTA_PTA6 _PTA.Bits.PTA6
#define PTA_PTA7 _PTA.Bits.PTA7
#define PTA_PTA0_MASK 0x01
#define PTA_PTA1_MASK 0x02
#define PTA_PTA2_MASK 0x04
#define PTA_PTA3_MASK 0x08
#define PTA_PTA4_MASK 0x10
#define PTA_PTA5_MASK 0x20
#define PTA_PTA6_MASK 0x40
#define PTA_PTA7_MASK 0x80
/*** PTB - Port B Data Register; 0x00000001 ***/
typedef union {
byte Byte;
struct {
byte PTB0 :1; /* Port B Data Bit 0 */
byte PTB1 :1; /* Port B Data Bit 1 */
byte PTB2 :1; /* Port B Data Bit 2 */
byte PTB3 :1; /* Port B Data Bit 3 */
byte PTB4 :1; /* Port B Data Bit 4 */
byte PTB5 :1; /* Port B Data Bit 5 */
byte PTB6 :1; /* Port B Data Bit 6 */
byte PTB7 :1; /* Port B Data Bit 7 */
} Bits;
} PTBSTR;
extern volatile PTBSTR _PTB @0x00000001;
#define PTB _PTB.Byte
#define PTB_PTB0 _PTB.Bits.PTB0
#define PTB_PTB1 _PTB.Bits.PTB1
#define PTB_PTB2 _PTB.Bits.PTB2
#define PTB_PTB3 _PTB.Bits.PTB3
#define PTB_PTB4 _PTB.Bits.PTB4
#define PTB_PTB5 _PTB.Bits.PTB5
#define PTB_PTB6 _PTB.Bits.PTB6
#define PTB_PTB7 _PTB.Bits.PTB7
#define PTB_PTB0_MASK 0x01
#define PTB_PTB1_MASK 0x02
#define PTB_PTB2_MASK 0x04
#define PTB_PTB3_MASK 0x08
#define PTB_PTB4_MASK 0x10
#define PTB_PTB5_MASK 0x20
#define PTB_PTB6_MASK 0x40
#define PTB_PTB7_MASK 0x80
/*** PTC - Port C Data Register; 0x00000002 ***/
typedef union {
byte Byte;
struct {
byte PTC0 :1; /* Port C Data Bit 0 */
byte PTC1 :1; /* Port C Data Bit 1 */
byte PTC2 :1; /* Port C Data Bit 2 */
byte PTC3 :1; /* Port C Data Bit 3 */
byte PTC4 :1; /* Port C Data Bit 4 */
byte PTC5 :1; /* Port C Data Bit 5 */
byte PTC6 :1; /* Port C Data Bit 6 */
byte PTC7 :1; /* Port C Data Bit 7 */
} Bits;
} PTCSTR;
extern volatile PTCSTR _PTC @0x00000002;
#define PTC _PTC.Byte
#define PTC_PTC0 _PTC.Bits.PTC0
#define PTC_PTC1 _PTC.Bits.PTC1
#define PTC_PTC2 _PTC.Bits.PTC2
#define PTC_PTC3 _PTC.Bits.PTC3
#define PTC_PTC4 _PTC.Bits.PTC4
#define PTC_PTC5 _PTC.Bits.PTC5
#define PTC_PTC6 _PTC.Bits.PTC6
#define PTC_PTC7 _PTC.Bits.PTC7
#define PTC_PTC0_MASK 0x01
#define PTC_PTC1_MASK 0x02
#define PTC_PTC2_MASK 0x04
#define PTC_PTC3_MASK 0x08
#define PTC_PTC4_MASK 0x10
#define PTC_PTC5_MASK 0x20
#define PTC_PTC6_MASK 0x40
#define PTC_PTC7_MASK 0x80
/*** PTD - Port D Data Register; 0x00000003 ***/
typedef union {
byte Byte;
struct {
byte PTD0 :1; /* Port D Data Bit 0 */
byte PTD1 :1; /* Port D Data Bit 1 */
byte PTD2 :1; /* Port D Data Bit 2 */
byte PTD3 :1; /* Port D Data Bit 3 */
byte PTD4 :1; /* Port D Data Bit 4 */
byte PTD5 :1; /* Port D Data Bit 5 */
byte PTD6 :1; /* Port D Data Bit 6 */
byte PTD7 :1; /* Port D Data Bit 7 */
} Bits;
} PTDSTR;
extern volatile PTDSTR _PTD @0x00000003;
#define PTD _PTD.Byte
#define PTD_PTD0 _PTD.Bits.PTD0
#define PTD_PTD1 _PTD.Bits.PTD1
#define PTD_PTD2 _PTD.Bits.PTD2
#define PTD_PTD3 _PTD.Bits.PTD3
#define PTD_PTD4 _PTD.Bits.PTD4
#define PTD_PTD5 _PTD.Bits.PTD5
#define PTD_PTD6 _PTD.Bits.PTD6
#define PTD_PTD7 _PTD.Bits.PTD7
#define PTD_PTD0_MASK 0x01
#define PTD_PTD1_MASK 0x02
#define PTD_PTD2_MASK 0x04
#define PTD_PTD3_MASK 0x08
#define PTD_PTD4_MASK 0x10
#define PTD_PTD5_MASK 0x20
#define PTD_PTD6_MASK 0x40
#define PTD_PTD7_MASK 0x80
/*** DDRA - Data Direction Register A; 0x00000004 ***/
typedef union {
byte Byte;
struct {
byte DDRA0 :1; /* Data Direction Register A Bit 0 */
byte DDRA1 :1; /* Data Direction Register A Bit 1 */
byte DDRA2 :1; /* Data Direction Register A Bit 2 */
byte DDRA3 :1; /* Data Direction Register A Bit 3 */
byte DDRA4 :1; /* Data Direction Register A Bit 4 */
byte DDRA5 :1; /* Data Direction Register A Bit 5 */
byte DDRA6 :1; /* Data Direction Register A Bit 6 */
byte DDRA7 :1; /* Data Direction Register A Bit 7 */
} Bits;
} DDRASTR;
extern volatile DDRASTR _DDRA @0x00000004;
#define DDRA _DDRA.Byte
#define DDRA_DDRA0 _DDRA.Bits.DDRA0
#define DDRA_DDRA1 _DDRA.Bits.DDRA1
#define DDRA_DDRA2 _DDRA.Bits.DDRA2
#define DDRA_DDRA3 _DDRA.Bits.DDRA3
#define DDRA_DDRA4 _DDRA.Bits.DDRA4
#define DDRA_DDRA5 _DDRA.Bits.DDRA5
#define DDRA_DDRA6 _DDRA.Bits.DDRA6
#define DDRA_DDRA7 _DDRA.Bits.DDRA7
#define DDRA_DDRA0_MASK 0x01
#define DDRA_DDRA1_MASK 0x02
#define DDRA_DDRA2_MASK 0x04
#define DDRA_DDRA3_MASK 0x08
#define DDRA_DDRA4_MASK 0x10
#define DDRA_DDRA5_MASK 0x20
#define DDRA_DDRA6_MASK 0x40
#define DDRA_DDRA7_MASK 0x80
/*** DDRB - Data Direction Register B; 0x00000005 ***/
typedef union {
byte Byte;
struct {
byte DDRB0 :1; /* Data Direction Register B Bit 0 */
byte DDRB1 :1; /* Data Direction Register B Bit 1 */
byte DDRB2 :1; /* Data Direction Register B Bit 2 */
byte DDRB3 :1; /* Data Direction Register B Bit 3 */
byte DDRB4 :1; /* Data Direction Register B Bit 4 */
byte DDRB5 :1; /* Data Direction Register B Bit 5 */
byte DDRB6 :1; /* Data Direction Register B Bit 6 */
byte DDRB7 :1; /* Data Direction Register B Bit 7 */
} Bits;
} DDRBSTR;
extern volatile DDRBSTR _DDRB @0x00000005;
#define DDRB _DDRB.Byte
#define DDRB_DDRB0 _DDRB.Bits.DDRB0
#define DDRB_DDRB1 _DDRB.Bits.DDRB1
#define DDRB_DDRB2 _DDRB.Bits.DDRB2
#define DDRB_DDRB3 _DDRB.Bits.DDRB3
#define DDRB_DDRB4 _DDRB.Bits.DDRB4
#define DDRB_DDRB5 _DDRB.Bits.DDRB5
#define DDRB_DDRB6 _DDRB.Bits.DDRB6
#define DDRB_DDRB7 _DDRB.Bits.DDRB7
#define DDRB_DDRB0_MASK 0x01
#define DDRB_DDRB1_MASK 0x02
#define DDRB_DDRB2_MASK 0x04
#define DDRB_DDRB3_MASK 0x08
#define DDRB_DDRB4_MASK 0x10
#define DDRB_DDRB5_MASK 0x20
#define DDRB_DDRB6_MASK 0x40
#define DDRB_DDRB7_MASK 0x80
/*** DDRC - Data Direction Register C; 0x00000006 ***/
typedef union {
byte Byte;
struct {
byte DDRC0 :1; /* Data Direction Register C Bit 0 */
byte DDRC1 :1; /* Data Direction Register C Bit 1 */
byte DDRC2 :1; /* Data Direction Register C Bit 2 */
byte DDRC3 :1; /* Data Direction Register C Bit 3 */
byte DDRC4 :1; /* Data Direction Register C Bit 4 */
byte DDRC5 :1; /* Data Direction Register C Bit 5 */
byte DDRC6 :1; /* Data Direction Register C Bit 6 */
byte DDRC7 :1; /* Data Direction Register C Bit 7 */
} Bits;
} DDRCSTR;
extern volatile DDRCSTR _DDRC @0x00000006;
#define DDRC _DDRC.Byte
#define DDRC_DDRC0 _DDRC.Bits.DDRC0
#define DDRC_DDRC1 _DDRC.Bits.DDRC1
#define DDRC_DDRC2 _DDRC.Bits.DDRC2
#define DDRC_DDRC3 _DDRC.Bits.DDRC3
#define DDRC_DDRC4 _DDRC.Bits.DDRC4
#define DDRC_DDRC5 _DDRC.Bits.DDRC5
#define DDRC_DDRC6 _DDRC.Bits.DDRC6
#define DDRC_DDRC7 _DDRC.Bits.DDRC7
#define DDRC_DDRC0_MASK 0x01
#define DDRC_DDRC1_MASK 0x02
#define DDRC_DDRC2_MASK 0x04
#define DDRC_DDRC3_MASK 0x08
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