cpu.c

基于FREEESCLAE LV8 的ADF7020通信程序

/** ###################################################################
**     THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
**     Filename  : Cpu.C
**     Project   : lv8
**     Processor : MC68HC908LV8CFA
**     Beantype  : MC68HC908LV8_52
**     Version   : Bean 01.078, Driver 01.36, CPU db: 2.89.060
**     Datasheet : MC68HC908LV8 Rev. 2 12/2005
**     Compiler  : CodeWarrior HC08 C Compiler
**     Date/Time : 2006-8-18, 20:00
**     Abstract  :
**         This bean "MC68HC908LV8_52" implements properties, methods,
**         and events of the CPU.
**     Settings  :
**         Clock setting
**             External clock      : 4.9152 MHz
**             CPU mode selection  : 0
**             Initialization interrupt priority : 1
**             Stop instruction enabled : no
**             LVI module          : yes
**
**         Speed modes
**             High speed clock    : Main clock frequency / 1
**             Internal bus clock  : 1.2288 MHz
**             Low speed mode      : Disabled
**             Slow speed mode     : Disabled
**     Contents  :
**         EnableInt  - void Cpu_EnableInt(void);
**         DisableInt - void Cpu_DisableInt(void);
**
**     (c) Copyright UNIS, spol. s r.o. 1997-2006
**     UNIS, spol. s r.o.
**     Jundrovska 33
**     624 00 Brno
**     Czech Republic
**     http      : www.processorexpert.com
**     mail      : [e-mail]
** ###################################################################*/

/* MODULE Cpu. */

#include "LCD1.h"
#include "PE_Types.h"
#include "PE_Error.h"
#include "PE_Const.h"
#include "IO_Map.h"
#include "Events.h"
#include "Cpu.h"

#define CGM_DELAY  0x13FFUL
/* Global variables */
volatile byte CCR_reg;                 /* Current CCR register */
byte CpuMode = HIGH_SPEED;             /* Current speed mode */

/*
** ===================================================================
**     Method      :  Cpu_Interrupt (bean MC68HC908LV8_52)
**
**     Description :
**         This ISR services unhandled interrupt vectors.
**         This method is internal. It is used by Processor Expert only.
** ===================================================================
*/
ISR(Cpu_Interrupt)
{
/* The following code is generated from the 'Unhandled interrupt code' */
/* property on the 'Build option tab' of the CPU bean                  */
/* (can be modified by the user)                                       */
  asm {
    swi
  }
}

/*
** ===================================================================
**     Method      :  Cpu_SWIInterrupt (bean MC68HC908LV8_52)
**
**     Description :
**         This ISR services the interrupt of the SWI instruction.
**         This method is internal. It is used by Processor Expert only.
** ===================================================================
*/
ISR(Cpu_SWIInterrupt)
{
  Cpu_OnSwINT();                       /* Invoke user event */
}

/*
** ===================================================================
**     Method      :  Cpu_DisableInt (bean MC68HC908LV8_52)
**
**     Description :
**         Disables maskable interrupts
**     Parameters  : None
**     Returns     : Nothing
** ===================================================================
*/
/*
void Cpu_DisableInt(void)

**      This method is implemented as macro in the header module. **
*/

/*
** ===================================================================
**     Method      :  Cpu_EnableInt (bean MC68HC908LV8_52)
**
**     Description :
**         Enables maskable interrupts
**     Parameters  : None
**     Returns     : Nothing
** ===================================================================
*/
/*
void Cpu_EnableInt(void)

**      This method is implemented as macro in the header module. **
*/

/*
** ===================================================================
**     Method      :  _EntryPoint (bean MC68HC908LV8_52)
**
**     Description :
**         Initializes the whole system like timing and so on. At the end 
**         of this function, the C startup is invoked to initialize stack,
**         memory areas and so on.
**         This method is internal. It is used by Processor Expert only.
** ===================================================================
*/
extern void _Startup(void);            /* Forward declaration of external compiler startup function */
#pragma NO_FRAME
#pragma NO_EXIT
void _EntryPoint(void)
{
  /*### MC68HC908LV8_52 - system initialization */

  /* Common initialization of the write once registers */
  /* CONFIG1: COPRS=0,LVISTOP=0,LVIRSTD=0,LVIPWRD=0,??=0,SSREC=0,STOP=0,COPD=1 */
  setReg8(CONFIG1, 0x01);               
  /* CONFIG2: STOP_XCLKEN=0,??=0,PEE=1,PDE=1,PCEH=1,PCEL=1,LVISEL1=0,LVISEL0=1 */
  setReg8(CONFIG2, 0x3D);               
  /*** End of PE initialization code after reset ***/

  __asm   jmp _Startup ;               /* Jump to C startup code */
}

/*
** ===================================================================
**     Method      :  PE_low_level_init (bean MC68HC908LV8_52)
**
**     Description :
**         Initializes beans and provides common register initialization. 
**         The method is called automatically as a part of the 
**         application initialization code.
**         This method is internal. It is used by Processor Expert only.
** ===================================================================
*/
void PE_low_level_init(void)
{
  /* Common initialization of the CPU registers */
  /* HDB: HDB5=1,HDB4=1,HDB3=1,HDB2=1 */
  setReg8Bits(HDB, 0x3C);               
  /* LVISR: LVIIE=0 */
  clrReg8Bits(LVISR, 0x40);             
  /* ### MC68HC908LV8_52 "Cpu" init code ... */
  /* ### Init_LCD "LCD1" init code ... */
  LCD1_Init();

  __EI();                              /* Enable interrupts */
}
/* Initialization of the CPU registers in FLASH */

/* END Cpu. */

/*
** ###################################################################
**
**     This file was created by UNIS Processor Expert 2.98 [03.80]
**     for the Freescale HC08 series of microcontrollers.
**
** ###################################################################
*/