📄 io_map.c
字号:
/*
** ###################################################################
**
** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
**
** Filename : IO_Map.C
**
** Project : LK24E
**
** Processor : MC68HC908LK24FAC_80
**
** Beantype : IO_Map
**
** Version : Driver 01.03
**
** Compiler : Metrowerks HC08 C Compiler
**
** Date/Time : 2004-1-3, 17:14
**
** Abstract :
**
** This bean "IO_Map" implements an IO devices mapping.
**
** Settings :
**
**
**
** Contents :
**
** No public methods
**
**
** (c) Copyright UNIS, spol. s r.o. 1997-2002
**
** UNIS, spol. s r.o.
** Jundrovska 33
** 624 00 Brno
** Czech Republic
**
** http : www.processorexpert.com
** mail : info@processorexpert.com
**
** ###################################################################
*/
/* Based on CPU DB MC68HC908LK24_80, version 2.87.026 */
#include "PE_types.h"
#include "IO_Map.h"
volatile ADCLKSTR _ADCLK; /* ADC Input Clock Register */
volatile ADRHSTR _ADRH; /* ADC Data Register High - Right-justified mode */
volatile ADRLSTR _ADRL; /* ADC Data Register Low - Right-justified mode */
volatile ADSCRSTR _ADSCR; /* ADC Status and Control Register */
volatile ALHRSTR _ALHR; /* Alarm Hour Register */
volatile ALMRSTR _ALMR; /* Alarm Minute Register */
volatile BRKHSTR _BRKH; /* Break Address Register High */
volatile BRKLSTR _BRKL; /* Break Address Register Low */
volatile BRKSCRSTR _BRKSCR; /* Break Status and Control Register */
volatile CONFIG1STR _CONFIG1; /* Configuration Register 1 */
volatile CONFIG2STR _CONFIG2; /* Configuration Register 2 */
volatile COPCTLSTR _COPCTL; /* COP Control Register */
volatile DAYRSTR _DAYR; /* Day Register */
volatile DDRASTR _DDRA; /* Data Direction Register A */
volatile DDRBSTR _DDRB; /* Data Direction Register B */
volatile DDRCSTR _DDRC; /* Data Direction Register C */
volatile DDRDSTR _DDRD; /* Data Direction Register D */
volatile DDRESTR _DDRE; /* Data Direction Register E */
volatile DDRFSTR _DDRF; /* Data Direction Register F */
volatile DOWRSTR _DOWR; /* Day-Of-Week Register */
volatile FLBPRSTR _FLBPR; /* FLASH Block Protect Register */
volatile FLCRSTR _FLCR; /* FLASH Control Register */
volatile HRRSTR _HRR; /* Hour Register */
volatile CHRRSTR _CHRR; /* Chronograph Data Register */
volatile INT1STR _INT1; /* Interrupt Status Register 1 */
volatile INT2STR _INT2; /* Interrupt Status Register 2 */
volatile INT3STR _INT3; /* Interrupt Status Register 3 */
volatile INTSCR1STR _INTSCR1; /* IRQ Status and Control Register */
volatile KBIERSTR _KBIER; /* Keyobard Interrupt Enable Register */
volatile KBSCRSTR _KBSCR; /* Keyboard Status and Control Register */
volatile LCDCLKSTR _LCDCLK; /* LCD Clock Register */
volatile LCDCRSTR _LCDCR; /* LCD Control Register */
volatile LDAT1STR _LDAT1; /* LCD Data Register 1 */
volatile LDAT10STR _LDAT10; /* LCD Data Register 10 */
volatile LDAT11STR _LDAT11; /* LCD Data Register 11 */
volatile LDAT12STR _LDAT12; /* LCD Data Register 12 */
volatile LDAT13STR _LDAT13; /* LCD Data Register 13 */
volatile LDAT14STR _LDAT14; /* LCD Data Register 14 */
volatile LDAT15STR _LDAT15; /* LCD Data Register 15 */
volatile LDAT16STR _LDAT16; /* LCD Data Register 16 */
volatile LDAT17STR _LDAT17; /* LCD Data Register 17 */
volatile LDAT2STR _LDAT2; /* LCD Data Register 2 */
volatile LDAT3STR _LDAT3; /* LCD Data Register 3 */
volatile LDAT4STR _LDAT4; /* LCD Data Register 4 */
volatile LDAT5STR _LDAT5; /* LCD Data Register 5 */
volatile LDAT6STR _LDAT6; /* LCD Data Register 6 */
volatile LDAT7STR _LDAT7; /* LCD Data Register 7 */
volatile LDAT8STR _LDAT8; /* LCD Data Register 8 */
volatile LDAT9STR _LDAT9; /* LCD Data Register 9 */
volatile LEDBSTR _LEDB; /* Port B LED Control Register */
volatile LEDCSTR _LEDC; /* Port C LED Control Register */
volatile LEDESTR _LEDE; /* Port E LED Control Register */
volatile LEDFSTR _LEDF; /* Port F LED Control Register */
volatile LVISRSTR _LVISR; /* LVI Status Register */
volatile MIMCRSTR _MIMCR; /* Multi-Master IIC Master Control Register */
volatile MINRSTR _MINR; /* Minute Register */
volatile MMADRSTR _MMADR; /* Multi-Master IIC Address Register */
volatile MMCRSTR _MMCR; /* Multi-Master IIC Control Register */
volatile MMDRRSTR _MMDRR; /* Multi-Master IIC Data Receive Register */
volatile MMDTRSTR _MMDTR; /* Multi-Master IIC Data Transmit Register */
volatile MMSRSTR _MMSR; /* Multi-Master IIC Status Register */
volatile MTHRSTR _MTHR; /* Monh Register */
volatile PBWCSTR _PBWC; /* PLL Bandwidth Control Register */
volatile PCTLSTR _PCTL; /* PLL Control Register */
volatile PMDSSTR _PMDS; /* PLL Reference Divider Select Register */
volatile PMRSSTR _PMRS; /* PLL VCO Range Select */
volatile PMSHSTR _PMSH; /* PLL Multiplier Select Register High */
volatile PMSLSTR _PMSL; /* PLL Multiplier Select Register Low */
volatile PTASTR _PTA; /* Port A Data Register */
volatile PTBSTR _PTB; /* Port B Data Register */
volatile PTCSTR _PTC; /* Port C Data Register */
volatile PTDSTR _PTD; /* Port D Data Register */
volatile PTESTR _PTE; /* Port E Data Register */
volatile PTFSTR _PTF; /* Port F Data Register */
volatile RTCCDATSTR _RTCCDAT; /* RTC Calibration Data Register */
volatile RTCCOMRSTR _RTCCOMR; /* RTC Calibration Control Register */
volatile RTCCR1STR _RTCCR1; /* RTC Control Register 1 */
volatile RTCCR2STR _RTCCR2; /* RTC Control Register 2 */
volatile RTCSRSTR _RTCSR; /* RTC Status Register */
volatile SBFCRSTR _SBFCR; /* SIM Break Flag Control Register */
volatile SBSRSTR _SBSR; /* SIM Break Status Register */
volatile SCBRSTR _SCBR; /* SCI Baud Rate Register */
volatile SCC1STR _SCC1; /* SCI Control Register 1 */
volatile SCC2STR _SCC2; /* SCI Control Register 2 */
volatile SCC3STR _SCC3; /* SCI Control Register 3 */
volatile SCDRSTR _SCDR; /* SCI Data Register */
volatile SCIRCRSTR _SCIRCR; /* SCI Infrared Control Register */
volatile SCS1STR _SCS1; /* SCI Status Register 1 */
volatile SCS2STR _SCS2; /* SCI Status Register 2 */
volatile SECRSTR _SECR; /* Second Register */
volatile SPCRSTR _SPCR; /* SPI Control Register */
volatile SPDRSTR _SPDR; /* SPI Data Register */
volatile SPSCRSTR _SPSCR; /* SPI Status and Control Register */
volatile SRSRSTR _SRSR; /* SIM Reset Status Register */
volatile T1CNTHSTR _T1CNTH; /* TIM1 Counter 1 Register High */
volatile T1CNTLSTR _T1CNTL; /* TIM1 Counter 1 Register Low */
volatile T1CH0HSTR _T1CH0H; /* TIM1 Channel 0 Register High */
volatile T1CH0LSTR _T1CH0L; /* TIM1 Channel 0 Register Low */
volatile T1CH1HSTR _T1CH1H; /* TIM1 Channel 1 Register High */
volatile T1CH1LSTR _T1CH1L; /* TIM1 Channel 1 Register Low */
volatile T1MODHSTR _T1MODH; /* TIM1 Counter 1 Modulo Register High */
volatile T1MODLSTR _T1MODL; /* TIM1 Counter 1 Modulo Register Low */
volatile T1SCSTR _T1SC; /* TIM1 Status and Control Register */
volatile T1SC0STR _T1SC0; /* TIM1 Channel 0 Status and Control Register */
volatile T1SC1STR _T1SC1; /* TIM1 Channel 1 Status and Control Register */
volatile T2CNTHSTR _T2CNTH; /* TIM2 Counter Register High */
volatile T2CNTLSTR _T2CNTL; /* TIM2 Counter Register Low */
volatile T2CH0HSTR _T2CH0H; /* TIM2 Channel 0 Register High */
volatile T2CH0LSTR _T2CH0L; /* TIM2 Channel 0 Register Low */
volatile T2CH1HSTR _T2CH1H; /* TIM2 Channel 1 Register High */
volatile T2CH1LSTR _T2CH1L; /* TIM2 Channel 1 Register Low */
volatile T2MODHSTR _T2MODH; /* TIM2 Counter Modulo Register High */
volatile T2MODLSTR _T2MODL; /* TIM2 Counter Modulo Register Low */
volatile T2SCSTR _T2SC; /* TIM2 Status and Control Register */
volatile T2SC0STR _T2SC0; /* TIM2 Channel 0 Status and Control Register */
volatile T2SC1STR _T2SC1; /* TIM2 Channel 1 Status and Control Register */
volatile YRRSTR _YRR; /* Year Register */
volatile ADRSTR _ADR; /* ADC Data Register - Right-justified */
volatile BRKSTR _BRK; /* Break Address Register */
volatile PMSSTR _PMS; /* PLL Multiplier Select Register */
volatile T1CNTSTR _T1CNT; /* TIM1 Counter 1 Register */
volatile T1CH0STR _T1CH0; /* TIM1 Channel 0 Register */
volatile T1CH1STR _T1CH1; /* TIM1 Channel 1 Register */
volatile T1MODSTR _T1MOD; /* TIM1 Counter 1 Modulo Register */
volatile T2CNTSTR _T2CNT; /* TIM2 Counter Register */
volatile T2CH0STR _T2CH0; /* TIM2 Channel 0 Register */
volatile T2CH1STR _T2CH1; /* TIM2 Channel 1 Register */
volatile T2MODSTR _T2MOD; /* TIM2 Counter Modulo Register */
/*
** ###################################################################
**
** This file was created by UNIS Processor Expert 03.23 for
** the Motorola HC08 series of microcontrollers.
**
** ###################################################################
*/
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -