📄 io_map.h
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byte BIT8 :1; /* TIM1 Channel Register BIT 8 */
byte BIT9 :1; /* TIM1 Channel Register BIT 9 */
byte BIT10 :1; /* TIM1 Channel Register BIT 10 */
byte BIT11 :1; /* TIM1 Channel Register BIT 11 */
byte BIT12 :1; /* TIM1 Channel Register BIT 12 */
byte BIT13 :1; /* TIM1 Channel Register BIT 13 */
byte BIT14 :1; /* TIM1 Channel Register BIT 14 */
byte BIT15 :1; /* TIM1 Channel Register BIT 15 */
} Bits;
struct {
byte grpBIT_8 :8;
} MergedBits;
} T1CH1HSTR;
extern volatile T1CH1HSTR _T1CH1H @0x00000029;
#define T1CH1H _T1CH1H.Byte
#define T1CH1H_BIT8 _T1CH1H.Bits.BIT8
#define T1CH1H_BIT9 _T1CH1H.Bits.BIT9
#define T1CH1H_BIT10 _T1CH1H.Bits.BIT10
#define T1CH1H_BIT11 _T1CH1H.Bits.BIT11
#define T1CH1H_BIT12 _T1CH1H.Bits.BIT12
#define T1CH1H_BIT13 _T1CH1H.Bits.BIT13
#define T1CH1H_BIT14 _T1CH1H.Bits.BIT14
#define T1CH1H_BIT15 _T1CH1H.Bits.BIT15
#define T1CH1H_BIT_8 _T1CH1H.MergedBits.grpBIT_8
#define T1CH1H_BIT T1CH1H_BIT_8
/*** T1CH1L - TIM1 Channel 1 Register Low ***/
typedef union {
byte Byte;
struct {
byte BIT0 :1; /* TIM1 Channel Register BIT 0 */
byte BIT1 :1; /* TIM1 Channel Register BIT 1 */
byte BIT2 :1; /* TIM1 Channel Register BIT 2 */
byte BIT3 :1; /* TIM1 Channel Register BIT 3 */
byte BIT4 :1; /* TIM1 Channel Register BIT 4 */
byte BIT5 :1; /* TIM1 Channel Register BIT 5 */
byte BIT6 :1; /* TIM1 Channel Register BIT 6 */
byte BIT7 :1; /* TIM1 Channel Register BIT 7 */
} Bits;
struct {
byte grpBIT :8;
} MergedBits;
} T1CH1LSTR;
extern volatile T1CH1LSTR _T1CH1L @0x0000002A;
#define T1CH1L _T1CH1L.Byte
#define T1CH1L_BIT0 _T1CH1L.Bits.BIT0
#define T1CH1L_BIT1 _T1CH1L.Bits.BIT1
#define T1CH1L_BIT2 _T1CH1L.Bits.BIT2
#define T1CH1L_BIT3 _T1CH1L.Bits.BIT3
#define T1CH1L_BIT4 _T1CH1L.Bits.BIT4
#define T1CH1L_BIT5 _T1CH1L.Bits.BIT5
#define T1CH1L_BIT6 _T1CH1L.Bits.BIT6
#define T1CH1L_BIT7 _T1CH1L.Bits.BIT7
#define T1CH1L_BIT _T1CH1L.MergedBits.grpBIT
/*** T2SC - TIM2 Status and Control Register ***/
typedef union {
byte Byte;
struct {
byte PS0 :1; /* Prescaler Select Bit 0 */
byte PS1 :1; /* Prescaler Select Bit 1 */
byte PS2 :1; /* Prescaler Select Bit 2 */
byte :1;
byte TRST :1; /* TIM2 Reset Bit */
byte TSTOP :1; /* TIM2 Stop Bit */
byte TOIE :1; /* TIM2 Overflow Interrupt Enable Bit */
byte TOF :1; /* TIM2 Overflow Flag Bit */
} Bits;
struct {
byte grpPS :3;
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
} MergedBits;
} T2SCSTR;
extern volatile T2SCSTR _T2SC @0x0000002B;
#define T2SC _T2SC.Byte
#define T2SC_PS0 _T2SC.Bits.PS0
#define T2SC_PS1 _T2SC.Bits.PS1
#define T2SC_PS2 _T2SC.Bits.PS2
#define T2SC_TRST _T2SC.Bits.TRST
#define T2SC_TSTOP _T2SC.Bits.TSTOP
#define T2SC_TOIE _T2SC.Bits.TOIE
#define T2SC_TOF _T2SC.Bits.TOF
#define T2SC_PS _T2SC.MergedBits.grpPS
/*** T2CNTH - TIM2 Counter Register High ***/
typedef union {
byte Byte;
struct {
byte BIT8 :1; /* TIM2 Counter Bit */
byte BIT9 :1; /* TIM2 Counter Bit */
byte BIT10 :1; /* TIM2 Counter Bit */
byte BIT11 :1; /* TIM2 Counter Bit */
byte BIT12 :1; /* TIM2 Counter Bit */
byte BIT13 :1; /* TIM2 Counter Bit */
byte BIT14 :1; /* TIM2 Counter Bit */
byte BIT15 :1; /* TIM2 Counter Bit */
} Bits;
struct {
byte grpBIT_8 :8;
} MergedBits;
} T2CNTHSTR;
extern volatile T2CNTHSTR _T2CNTH @0x0000002C;
#define T2CNTH _T2CNTH.Byte
#define T2CNTH_BIT8 _T2CNTH.Bits.BIT8
#define T2CNTH_BIT9 _T2CNTH.Bits.BIT9
#define T2CNTH_BIT10 _T2CNTH.Bits.BIT10
#define T2CNTH_BIT11 _T2CNTH.Bits.BIT11
#define T2CNTH_BIT12 _T2CNTH.Bits.BIT12
#define T2CNTH_BIT13 _T2CNTH.Bits.BIT13
#define T2CNTH_BIT14 _T2CNTH.Bits.BIT14
#define T2CNTH_BIT15 _T2CNTH.Bits.BIT15
#define T2CNTH_BIT_8 _T2CNTH.MergedBits.grpBIT_8
#define T2CNTH_BIT T2CNTH_BIT_8
/*** T2CNTL - TIM2 Counter Register Low ***/
typedef union {
byte Byte;
struct {
byte BIT0 :1; /* TIM2 Counter Register Bit 0 */
byte BIT1 :1; /* TIM2 Counter Register Bit 1 */
byte BIT2 :1; /* TIM2 Counter Register Bit 2 */
byte BIT3 :1; /* TIM2 Counter Register Bit 3 */
byte BIT4 :1; /* TIM2 Counter Register Bit 4 */
byte BIT5 :1; /* TIM2 Counter Register Bit 5 */
byte BIT6 :1; /* TIM2 Counter Register Bit 6 */
byte BIT7 :1; /* TIM2 Counter Register Bit 7 */
} Bits;
struct {
byte grpBIT :8;
} MergedBits;
} T2CNTLSTR;
extern volatile T2CNTLSTR _T2CNTL @0x0000002D;
#define T2CNTL _T2CNTL.Byte
#define T2CNTL_BIT0 _T2CNTL.Bits.BIT0
#define T2CNTL_BIT1 _T2CNTL.Bits.BIT1
#define T2CNTL_BIT2 _T2CNTL.Bits.BIT2
#define T2CNTL_BIT3 _T2CNTL.Bits.BIT3
#define T2CNTL_BIT4 _T2CNTL.Bits.BIT4
#define T2CNTL_BIT5 _T2CNTL.Bits.BIT5
#define T2CNTL_BIT6 _T2CNTL.Bits.BIT6
#define T2CNTL_BIT7 _T2CNTL.Bits.BIT7
#define T2CNTL_BIT _T2CNTL.MergedBits.grpBIT
/*** T2MODH - TIM2 Counter Modulo Register High ***/
typedef union {
byte Byte;
struct {
byte BIT8 :1; /* TIM2 Counter Modulo Bit */
byte BIT9 :1; /* TIM2 Counter Modulo Bit */
byte BIT10 :1; /* TIM2 Counter Modulo Bit */
byte BIT11 :1; /* TIM2 Counter Modulo Bit */
byte BIT12 :1; /* TIM2 Counter Modulo Bit */
byte BIT13 :1; /* TIM2 Counter Modulo Bit */
byte BIT14 :1; /* TIM2 Counter Modulo Bit */
byte BIT15 :1; /* TIM2 Counter Modulo Bit */
} Bits;
struct {
byte grpBIT_8 :8;
} MergedBits;
} T2MODHSTR;
extern volatile T2MODHSTR _T2MODH @0x0000002E;
#define T2MODH _T2MODH.Byte
#define T2MODH_BIT8 _T2MODH.Bits.BIT8
#define T2MODH_BIT9 _T2MODH.Bits.BIT9
#define T2MODH_BIT10 _T2MODH.Bits.BIT10
#define T2MODH_BIT11 _T2MODH.Bits.BIT11
#define T2MODH_BIT12 _T2MODH.Bits.BIT12
#define T2MODH_BIT13 _T2MODH.Bits.BIT13
#define T2MODH_BIT14 _T2MODH.Bits.BIT14
#define T2MODH_BIT15 _T2MODH.Bits.BIT15
#define T2MODH_BIT_8 _T2MODH.MergedBits.grpBIT_8
#define T2MODH_BIT T2MODH_BIT_8
/*** T2MODL - TIM2 Counter Modulo Register Low ***/
typedef union {
byte Byte;
struct {
byte BIT0 :1; /* TIM2 Counter Modulo Bit */
byte BIT1 :1; /* TIM2 Counter Modulo Bit */
byte BIT2 :1; /* TIM2 Counter Modulo Bit */
byte BIT3 :1; /* TIM2 Counter Modulo Bit */
byte BIT4 :1; /* TIM2 Counter Modulo Bit */
byte BIT5 :1; /* TIM2 Counter Modulo Bit */
byte BIT6 :1; /* TIM2 Counter Modulo Bit */
byte BIT7 :1; /* TIM2 Counter Modulo Bit */
} Bits;
struct {
byte grpBIT :8;
} MergedBits;
} T2MODLSTR;
extern volatile T2MODLSTR _T2MODL @0x0000002F;
#define T2MODL _T2MODL.Byte
#define T2MODL_BIT0 _T2MODL.Bits.BIT0
#define T2MODL_BIT1 _T2MODL.Bits.BIT1
#define T2MODL_BIT2 _T2MODL.Bits.BIT2
#define T2MODL_BIT3 _T2MODL.Bits.BIT3
#define T2MODL_BIT4 _T2MODL.Bits.BIT4
#define T2MODL_BIT5 _T2MODL.Bits.BIT5
#define T2MODL_BIT6 _T2MODL.Bits.BIT6
#define T2MODL_BIT7 _T2MODL.Bits.BIT7
#define T2MODL_BIT _T2MODL.MergedBits.grpBIT
/*** T2SC0 - TIM2 Channel 0 Status and Control Register ***/
typedef union {
byte Byte;
struct {
byte CH0MAX :1; /* Channel 0 Maximum Duty Cycle Bit */
byte TOV0 :1; /* Toggle-On-Overflow Bit */
byte ELS0A :1; /* Edge/Level Select Bit A */
byte ELS0B :1; /* Edge/Level Select Bit B */
byte MS0A :1; /* Mode Select Bit A */
byte MS0B :1; /* Mode Select Bit B */
byte CH0IE :1; /* Channel 0 Interrupt Enable Bit */
byte CH0F :1; /* Channel 0 Flag Bit */
} Bits;
} T2SC0STR;
extern volatile T2SC0STR _T2SC0 @0x00000030;
#define T2SC0 _T2SC0.Byte
#define T2SC0_CH0MAX _T2SC0.Bits.CH0MAX
#define T2SC0_TOV0 _T2SC0.Bits.TOV0
#define T2SC0_ELS0A _T2SC0.Bits.ELS0A
#define T2SC0_ELS0B _T2SC0.Bits.ELS0B
#define T2SC0_MS0A _T2SC0.Bits.MS0A
#define T2SC0_MS0B _T2SC0.Bits.MS0B
#define T2SC0_CH0IE _T2SC0.Bits.CH0IE
#define T2SC0_CH0F _T2SC0.Bits.CH0F
/*** T2CH0H - TIM2 Channel 0 Register High ***/
typedef union {
byte Byte;
struct {
byte BIT8 :1; /* TIM2 Channel Register BIT 8 */
byte BIT9 :1; /* TIM2 Channel Register BIT 9 */
byte BIT10 :1; /* TIM2 Channel Register BIT 10 */
byte BIT11 :1; /* TIM2 Channel Register BIT 11 */
byte BIT12 :1; /* TIM2 Channel Register BIT 12 */
byte BIT13 :1; /* TIM2 Channel Register BIT 13 */
byte BIT14 :1; /* TIM2 Channel Register BIT 14 */
byte BIT15 :1; /* TIM2 Channel Register BIT 15 */
} Bits;
struct {
byte grpBIT_8 :8;
} MergedBits;
} T2CH0HSTR;
extern volatile T2CH0HSTR _T2CH0H @0x00000031;
#define T2CH0H _T2CH0H.Byte
#define T2CH0H_BIT8 _T2CH0H.Bits.BIT8
#define T2CH0H_BIT9 _T2CH0H.Bits.BIT9
#define T2CH0H_BIT10 _T2CH0H.Bits.BIT10
#define T2CH0H_BIT11 _T2CH0H.Bits.BIT11
#define T2CH0H_BIT12 _T2CH0H.Bits.BIT12
#define T2CH0H_BIT13 _T2CH0H.Bits.BIT13
#define T2CH0H_BIT14 _T2CH0H.Bits.BIT14
#define T2CH0H_BIT15 _T2CH0H.Bits.BIT15
#define T2CH0H_BIT_8 _T2CH0H.MergedBits.grpBIT_8
#define T2CH0H_BIT T2CH0H_BIT_8
/*** T2CH0L - TIM2 Channel 0 Register Low ***/
typedef union {
byte Byte;
struct {
byte BIT0 :1; /* TIM2 Channel Register BIT 0 */
byte BIT1 :1; /* TIM2 Channel Register BIT 1 */
byte BIT2 :1; /* TIM2 Channel Register BIT 2 */
byte BIT3 :1; /* TIM2 Channel Register BIT 3 */
byte BIT4 :1; /* TIM2 Channel Register BIT 4 */
byte BIT5 :1; /* TIM2 Channel Register BIT 5 */
byte BIT6 :1; /* TIM2 Channel Register BIT 6 */
byte BIT7 :1; /* TIM2 Channel Register BIT 7 */
} Bits;
struct {
byte grpBIT :8;
} MergedBits;
} T2CH0LSTR;
extern volatile T2CH0LSTR _T2CH0L @0x00000032;
#define T2CH0L _T2CH0L.Byte
#define T2CH0L_BIT0 _T2CH0L.Bits.BIT0
#define T2CH0L_BIT1 _T2CH0L.Bits.BIT1
#define T2CH0L_BIT2 _T2CH0L.Bits.BIT2
#define T2CH0L_BIT3 _T2CH0L.Bits.BIT3
#define T2CH0L_BIT4 _T2CH0L.Bits.BIT4
#define T2CH0L_BIT5 _T2CH0L.Bits.BIT5
#define T2CH0L_BIT6 _T2CH0L.Bits.BIT6
#define T2CH0L_BIT7 _T2CH0L.Bits.BIT7
#define T2CH0L_BIT _T2CH0L.MergedBits.grpBIT
/*** T2SC1 - TIM2 Channel 1 Status and Control Register ***/
typedef union {
byte Byte;
struct {
byte CH1MAX :1; /* Channel 1 Maximum Duty Cycle Bit */
byte TOV1 :1; /* Toggle-On-Overflow Bit */
byte ELS1A :1; ⌨️ 快捷键说明
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