📄 io_map.h
字号:
byte :1;
byte :1;
byte :1;
} Bits;
} INTSCR1STR;
extern volatile INTSCR1STR _INTSCR1 @0x0000001E;
#define INTSCR1 _INTSCR1.Byte
#define INTSCR1_MODE _INTSCR1.Bits.MODE
#define INTSCR1_IMASK _INTSCR1.Bits.IMASK
#define INTSCR1_ACK _INTSCR1.Bits.ACK
#define INTSCR1_IRQF _INTSCR1.Bits.IRQF
/*** CONFIG1 - Configuration Register 1 ***/
typedef union {
byte Byte;
struct {
byte COPD :1; /* COP Disable Bit */
byte STOP :1; /* STOP Instruction Enable Bit */
byte SSREC :1; /* Short Stop Recovery Bit */
byte :1;
byte LVIPWRD :1; /* LVI Power Disable Bit */
byte LVIRSTD :1; /* LVI Reset Disable Bit */
byte LVISTOP :1; /* LVI Enable in Stop Mode Bit */
byte COPRS :1; /* COP rate Select Bit */
} Bits;
} CONFIG1STR;
extern volatile CONFIG1STR _CONFIG1 @0x0000001F;
#define CONFIG1 _CONFIG1.Byte
#define CONFIG1_COPD _CONFIG1.Bits.COPD
#define CONFIG1_STOP _CONFIG1.Bits.STOP
#define CONFIG1_SSREC _CONFIG1.Bits.SSREC
#define CONFIG1_LVIPWRD _CONFIG1.Bits.LVIPWRD
#define CONFIG1_LVIRSTD _CONFIG1.Bits.LVIRSTD
#define CONFIG1_LVISTOP _CONFIG1.Bits.LVISTOP
#define CONFIG1_COPRS _CONFIG1.Bits.COPRS
/*** T1SC - TIM1 Status and Control Register ***/
typedef union {
byte Byte;
struct {
byte PS0 :1; /* Prescaler Select Bit 0 */
byte PS1 :1; /* Prescaler Select Bit 1 */
byte PS2 :1; /* Prescaler Select Bit 2 */
byte :1;
byte TRST :1; /* TIM1 Reset Bit */
byte TSTOP :1; /* TIM1 Stop Bit */
byte TOIE :1; /* TIM1 Overflow Interrupt Enable Bit */
byte TOF :1; /* TIM1 Overflow Flag Bit */
} Bits;
struct {
byte grpPS :3;
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
} MergedBits;
} T1SCSTR;
extern volatile T1SCSTR _T1SC @0x00000020;
#define T1SC _T1SC.Byte
#define T1SC_PS0 _T1SC.Bits.PS0
#define T1SC_PS1 _T1SC.Bits.PS1
#define T1SC_PS2 _T1SC.Bits.PS2
#define T1SC_TRST _T1SC.Bits.TRST
#define T1SC_TSTOP _T1SC.Bits.TSTOP
#define T1SC_TOIE _T1SC.Bits.TOIE
#define T1SC_TOF _T1SC.Bits.TOF
#define T1SC_PS _T1SC.MergedBits.grpPS
/*** T1CNTH - TIM1 Counter 1 Register High ***/
typedef union {
byte Byte;
struct {
byte BIT8 :1; /* TIM Counter Register BIT 8 */
byte BIT9 :1; /* TIM Counter Register BIT 9 */
byte BIT10 :1; /* TIM Counter Register BIT 10 */
byte BIT11 :1; /* TIM Counter Register BIT 11 */
byte BIT12 :1; /* TIM Counter Register BIT 12 */
byte BIT13 :1; /* TIM Counter Register BIT 13 */
byte BIT14 :1; /* TIM Counter Register BIT 14 */
byte BIT15 :1; /* TIM Counter Register BIT 15 */
} Bits;
struct {
byte grpBIT_8 :8;
} MergedBits;
} T1CNTHSTR;
extern volatile T1CNTHSTR _T1CNTH @0x00000021;
#define T1CNTH _T1CNTH.Byte
#define T1CNTH_BIT8 _T1CNTH.Bits.BIT8
#define T1CNTH_BIT9 _T1CNTH.Bits.BIT9
#define T1CNTH_BIT10 _T1CNTH.Bits.BIT10
#define T1CNTH_BIT11 _T1CNTH.Bits.BIT11
#define T1CNTH_BIT12 _T1CNTH.Bits.BIT12
#define T1CNTH_BIT13 _T1CNTH.Bits.BIT13
#define T1CNTH_BIT14 _T1CNTH.Bits.BIT14
#define T1CNTH_BIT15 _T1CNTH.Bits.BIT15
#define T1CNTH_BIT_8 _T1CNTH.MergedBits.grpBIT_8
#define T1CNTH_BIT T1CNTH_BIT_8
/*** T1CNTL - TIM1 Counter 1 Register Low ***/
typedef union {
byte Byte;
struct {
byte BIT0 :1; /* TIM Counter Register BIT 0 */
byte BIT1 :1; /* TIM Counter Register BIT 1 */
byte BIT2 :1; /* TIM Counter Register BIT 2 */
byte BIT3 :1; /* TIM Counter Register BIT 3 */
byte BIT4 :1; /* TIM Counter Register BIT 4 */
byte BIT5 :1; /* TIM Counter Register BIT 5 */
byte BIT6 :1; /* TIM Counter Register BIT 6 */
byte BIT7 :1; /* TIM Counter Register BIT 7 */
} Bits;
struct {
byte grpBIT :8;
} MergedBits;
} T1CNTLSTR;
extern volatile T1CNTLSTR _T1CNTL @0x00000022;
#define T1CNTL _T1CNTL.Byte
#define T1CNTL_BIT0 _T1CNTL.Bits.BIT0
#define T1CNTL_BIT1 _T1CNTL.Bits.BIT1
#define T1CNTL_BIT2 _T1CNTL.Bits.BIT2
#define T1CNTL_BIT3 _T1CNTL.Bits.BIT3
#define T1CNTL_BIT4 _T1CNTL.Bits.BIT4
#define T1CNTL_BIT5 _T1CNTL.Bits.BIT5
#define T1CNTL_BIT6 _T1CNTL.Bits.BIT6
#define T1CNTL_BIT7 _T1CNTL.Bits.BIT7
#define T1CNTL_BIT _T1CNTL.MergedBits.grpBIT
/*** T1MODH - TIM1 Counter 1 Modulo Register High ***/
typedef union {
byte Byte;
struct {
byte BIT8 :1; /* TIM1 Counter Modulo Bit */
byte BIT9 :1; /* TIM1 Counter Modulo Bit */
byte BIT10 :1; /* TIM1 Counter Modulo Bit */
byte BIT11 :1; /* TIM1 Counter Modulo Bit */
byte BIT12 :1; /* TIM1 Counter Modulo Bit */
byte BIT13 :1; /* TIM1 Counter Modulo Bit */
byte BIT14 :1; /* TIM1 Counter Modulo Bit */
byte BIT15 :1; /* TIM1 Counter Modulo Bit */
} Bits;
struct {
byte grpBIT_8 :8;
} MergedBits;
} T1MODHSTR;
extern volatile T1MODHSTR _T1MODH @0x00000023;
#define T1MODH _T1MODH.Byte
#define T1MODH_BIT8 _T1MODH.Bits.BIT8
#define T1MODH_BIT9 _T1MODH.Bits.BIT9
#define T1MODH_BIT10 _T1MODH.Bits.BIT10
#define T1MODH_BIT11 _T1MODH.Bits.BIT11
#define T1MODH_BIT12 _T1MODH.Bits.BIT12
#define T1MODH_BIT13 _T1MODH.Bits.BIT13
#define T1MODH_BIT14 _T1MODH.Bits.BIT14
#define T1MODH_BIT15 _T1MODH.Bits.BIT15
#define T1MODH_BIT_8 _T1MODH.MergedBits.grpBIT_8
#define T1MODH_BIT T1MODH_BIT_8
/*** T1MODL - TIM1 Counter 1 Modulo Register Low ***/
typedef union {
byte Byte;
struct {
byte BIT0 :1; /* TIM1 Counter Modulo Bit */
byte BIT1 :1; /* TIM1 Counter Modulo Bit */
byte BIT2 :1; /* TIM1 Counter Modulo Bit */
byte BIT3 :1; /* TIM1 Counter Modulo Bit */
byte BIT4 :1; /* TIM1 Counter Modulo Bit */
byte BIT5 :1; /* TIM1 Counter Modulo Bit */
byte BIT6 :1; /* TIM1 Counter Modulo Bit */
byte BIT7 :1; /* TIM1 Counter Modulo Bit */
} Bits;
struct {
byte grpBIT :8;
} MergedBits;
} T1MODLSTR;
extern volatile T1MODLSTR _T1MODL @0x00000024;
#define T1MODL _T1MODL.Byte
#define T1MODL_BIT0 _T1MODL.Bits.BIT0
#define T1MODL_BIT1 _T1MODL.Bits.BIT1
#define T1MODL_BIT2 _T1MODL.Bits.BIT2
#define T1MODL_BIT3 _T1MODL.Bits.BIT3
#define T1MODL_BIT4 _T1MODL.Bits.BIT4
#define T1MODL_BIT5 _T1MODL.Bits.BIT5
#define T1MODL_BIT6 _T1MODL.Bits.BIT6
#define T1MODL_BIT7 _T1MODL.Bits.BIT7
#define T1MODL_BIT _T1MODL.MergedBits.grpBIT
/*** T1SC0 - TIM1 Channel 0 Status and Control Register ***/
typedef union {
byte Byte;
struct {
byte CH0MAX :1; /* Channel 0 Maximum Duty Cycle Bit */
byte TOV0 :1; /* Toggle-On-Overflow Bit */
byte ELS0A :1; /* Edge/Level Select Bit A */
byte ELS0B :1; /* Edge/Level Select Bit B */
byte MS0A :1; /* Mode Select Bit A */
byte MS0B :1; /* Mode Select Bit B */
byte CH0IE :1; /* Channel 0 Interrupt Enable Bit */
byte CH0F :1; /* Channel 0 Flag Bit */
} Bits;
} T1SC0STR;
extern volatile T1SC0STR _T1SC0 @0x00000025;
#define T1SC0 _T1SC0.Byte
#define T1SC0_CH0MAX _T1SC0.Bits.CH0MAX
#define T1SC0_TOV0 _T1SC0.Bits.TOV0
#define T1SC0_ELS0A _T1SC0.Bits.ELS0A
#define T1SC0_ELS0B _T1SC0.Bits.ELS0B
#define T1SC0_MS0A _T1SC0.Bits.MS0A
#define T1SC0_MS0B _T1SC0.Bits.MS0B
#define T1SC0_CH0IE _T1SC0.Bits.CH0IE
#define T1SC0_CH0F _T1SC0.Bits.CH0F
/*** T1CH0H - TIM1 Channel 0 Register High ***/
typedef union {
byte Byte;
struct {
byte BIT8 :1; /* TIM1 Channel Register BIT 8 */
byte BIT9 :1; /* TIM1 Channel Register BIT 9 */
byte BIT10 :1; /* TIM1 Channel Register BIT 10 */
byte BIT11 :1; /* TIM1 Channel Register BIT 11 */
byte BIT12 :1; /* TIM1 Channel Register BIT 12 */
byte BIT13 :1; /* TIM1 Channel Register BIT 13 */
byte BIT14 :1; /* TIM1 Channel Register BIT 14 */
byte BIT15 :1; /* TIM1 Channel Register BIT 15 */
} Bits;
struct {
byte grpBIT_8 :8;
} MergedBits;
} T1CH0HSTR;
extern volatile T1CH0HSTR _T1CH0H @0x00000026;
#define T1CH0H _T1CH0H.Byte
#define T1CH0H_BIT8 _T1CH0H.Bits.BIT8
#define T1CH0H_BIT9 _T1CH0H.Bits.BIT9
#define T1CH0H_BIT10 _T1CH0H.Bits.BIT10
#define T1CH0H_BIT11 _T1CH0H.Bits.BIT11
#define T1CH0H_BIT12 _T1CH0H.Bits.BIT12
#define T1CH0H_BIT13 _T1CH0H.Bits.BIT13
#define T1CH0H_BIT14 _T1CH0H.Bits.BIT14
#define T1CH0H_BIT15 _T1CH0H.Bits.BIT15
#define T1CH0H_BIT_8 _T1CH0H.MergedBits.grpBIT_8
#define T1CH0H_BIT T1CH0H_BIT_8
/*** T1CH0L - TIM1 Channel 0 Register Low ***/
typedef union {
byte Byte;
struct {
byte BIT0 :1; /* TIM1 Channel Register BIT 0 */
byte BIT1 :1; /* TIM1 Channel Register BIT 1 */
byte BIT2 :1; /* TIM1 Channel Register BIT 2 */
byte BIT3 :1; /* TIM1 Channel Register BIT 3 */
byte BIT4 :1; /* TIM1 Channel Register BIT 4 */
byte BIT5 :1; /* TIM1 Channel Register BIT 5 */
byte BIT6 :1; /* TIM1 Channel Register BIT 6 */
byte BIT7 :1; /* TIM1 Channel Register BIT 7 */
} Bits;
struct {
byte grpBIT :8;
} MergedBits;
} T1CH0LSTR;
extern volatile T1CH0LSTR _T1CH0L @0x00000027;
#define T1CH0L _T1CH0L.Byte
#define T1CH0L_BIT0 _T1CH0L.Bits.BIT0
#define T1CH0L_BIT1 _T1CH0L.Bits.BIT1
#define T1CH0L_BIT2 _T1CH0L.Bits.BIT2
#define T1CH0L_BIT3 _T1CH0L.Bits.BIT3
#define T1CH0L_BIT4 _T1CH0L.Bits.BIT4
#define T1CH0L_BIT5 _T1CH0L.Bits.BIT5
#define T1CH0L_BIT6 _T1CH0L.Bits.BIT6
#define T1CH0L_BIT7 _T1CH0L.Bits.BIT7
#define T1CH0L_BIT _T1CH0L.MergedBits.grpBIT
/*** T1SC1 - TIM1 Channel 1 Status and Control Register ***/
typedef union {
byte Byte;
struct {
byte CH1MAX :1; /* Channel 1 Maximum Duty Cycle Bit */
byte TOV1 :1; /* Toggle-On-Overflow Bit */
byte ELS1A :1; /* Edge/Level Select Bit A */
byte ELS1B :1; /* Edge/Level Select Bit B */
byte MS1A :1; /* Mode Select Bit A */
byte :1;
byte CH1IE :1; /* Channel 1 Interrupt Enable Bit */
byte CH1F :1; /* Channel 1 Flag Bit */
} Bits;
} T1SC1STR;
extern volatile T1SC1STR _T1SC1 @0x00000028;
#define T1SC1 _T1SC1.Byte
#define T1SC1_CH1MAX _T1SC1.Bits.CH1MAX
#define T1SC1_TOV1 _T1SC1.Bits.TOV1
#define T1SC1_ELS1A _T1SC1.Bits.ELS1A
#define T1SC1_ELS1B _T1SC1.Bits.ELS1B
#define T1SC1_MS1A _T1SC1.Bits.MS1A
#define T1SC1_CH1IE _T1SC1.Bits.CH1IE
#define T1SC1_CH1F _T1SC1.Bits.CH1F
/*** T1CH1H - TIM1 Channel 1 Register High ***/
typedef union {
byte Byte;
struct {
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -