📄 evbradio.h
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/*
V0.1 Initial Release 10/July/2006 RBR
Port over Tmote 23/December/2006 RS
*/
#ifndef EVBRADIO_H
#define EVBRADIO_H
//-------------------------------------------------------------------------------------------------------
// CC2420 register constants
#define CC2420_SNOP 0x00
#define CC2420_SXOSCON 0x01
#define CC2420_STXCAL 0x02
#define CC2420_SRXON 0x03
#define CC2420_STXON 0x04
#define CC2420_STXONCCA 0x05
#define CC2420_SRFOFF 0x06
#define CC2420_SXOSCOFF 0x07
#define CC2420_SFLUSHRX 0x08
#define CC2420_SFLUSHTX 0x09
#define CC2420_SACK 0x0A
#define CC2420_SACKPEND 0x0B
#define CC2420_SRXDEC 0x0C
#define CC2420_STXENC 0x0D
#define CC2420_SAES 0x0E
#define CC2420_MAIN 0x10
#define CC2420_MDMCTRL0 0x11
#define CC2420_MDMCTRL1 0x12
#define CC2420_RSSI 0x13
#define CC2420_SYNCWORD 0x14
#define CC2420_TXCTRL 0x15
#define CC2420_RXCTRL0 0x16
#define CC2420_RXCTRL1 0x17
#define CC2420_FSCTRL 0x18
#define CC2420_SECCTRL0 0x19
#define CC2420_SECCTRL1 0x1A
#define CC2420_BATTMON 0x1B
#define CC2420_IOCFG0 0x1C
#define CC2420_IOCFG1 0x1D
#define CC2420_MANFIDL 0x1E
#define CC2420_MANFIDH 0x1F
#define CC2420_FSMTC 0x20
#define CC2420_MANAND 0x21
#define CC2420_MANOR 0x22
#define CC2420_AGCCTRL 0x23
#define CC2420_AGCTST0 0x24
#define CC2420_AGCTST1 0x25
#define CC2420_AGCTST2 0x26
#define CC2420_FSTST0 0x27
#define CC2420_FSTST1 0x28
#define CC2420_FSTST2 0x29
#define CC2420_FSTST3 0x2A
#define CC2420_RXBPFTST 0x2B
#define CC2420_FSMSTATE 0x2C
#define CC2420_ADCTST 0x2D
#define CC2420_DACTST 0x2E
#define CC2420_TOPTST 0x2F
#define CC2420_RESERVED 0x30
#define CC2420_TXFIFO 0x3E
#define CC2420_RXFIFO 0x3F
//-------------------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------------------
// Memory
// Sizes
#define CC2420_RAM_SIZE 368
#define CC2420_FIFO_SIZE 128
// Addresses
#define CC2420RAM_TXFIFO 0x000
#define CC2420RAM_RXFIFO 0x080
#define CC2420RAM_KEY0 0x100
#define CC2420RAM_RXNONCE 0x110
#define CC2420RAM_SABUF 0x120
#define CC2420RAM_KEY1 0x130
#define CC2420RAM_TXNONCE 0x140
#define CC2420RAM_CBCSTATE 0x150
#define CC2420RAM_IEEEADDR 0x160
#define CC2420RAM_PANID 0x168
#define CC2420RAM_SHORTADDR 0x16A
//-------------------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------------------
// Status byte
#define CC2420_XOSC16M_STABLE 6
#define CC2420_TX_UNDERFLOW 5
#define CC2420_ENC_BUSY 4
#define CC2420_TX_ACTIVE 3
#define CC2420_LOCK 2
#define CC2420_RSSI_VALID 1
//-------------------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------------------
// SECCTRL0
#define CC2420_SECCTRL0_NO_SECURITY 0x0000
#define CC2420_SECCTRL0_CBC_MAC 0x0001
#define CC2420_SECCTRL0_CTR 0x0002
#define CC2420_SECCTRL0_CCM 0x0003
#define CC2420_SECCTRL0_SEC_M_IDX 2
#define CC2420_SECCTRL0_RXKEYSEL0 0x0000
#define CC2420_SECCTRL0_RXKEYSEL1 0x0020
#define CC2420_SECCTRL0_TXKEYSEL0 0x0000
#define CC2420_SECCTRL0_TXKEYSEL1 0x0040
#define CC2420_SECCTRL0_SEC_CBC_HEAD 0x0100
#define CC2420_SECCTRL0_RXFIFO_PROTECTION 0x0200
//-------------------------------------------------------------------------------------------------------
// RSSI to Energy Detection conversion
// RSSI_OFFSET defines the RSSI level where the PLME.ED generates a zero-value
#define RSSI_OFFSET -38
#define RSSI_2_ED(rssi) ((rssi) < RSSI_OFFSET ? 0 : ((rssi) - (RSSI_OFFSET)))
#define ED_2_LQI(ed) (((ed) > 63 ? 255 : ((ed) << 2)))
//-------------------------------------------------------------------------------------------------------
/*
* SPI bus configuration for the TMote Sky.
*/
#define SCK 1 /* P3.1 - Output: SPI Serial Clock (SCLK) */
#define MOSI 2 /* P3.2 - Output: SPI Master out - slave in (MOSI) */
#define MISO 3 /* P3.3 - Input: SPI Master in - slave out (MISO) */
/*
* SPI bus - CC2420 pin configuration.
*/
#define FIFO_P 0 /* P1.0 - Input: FIFOP from CC2420 */
#define FIFO 3 /* P1.3 - Input: FIFO from CC2420 */
#define CCA 4 /* P1.4 - Input: CCA from CC2420 */
#define SFD 1 /* P4.1 - Input: SFD from CC2420 */
#define CSN 2 /* P4.2 - Output: SPI Chip Select (CS_N) */
#define VREG_EN 5 /* P4.5 - Output: VREG_EN to CC2420 */
#define RESET_N 6 /* P4.6 - Output: RESET_N to CC2420 */
/* Pin status. */
#define FIFO_IS_1 (!!(P1IN & BV(FIFO)))
#define CCA_IS_1 (!!(P1IN & BV(CCA) ))
#define RESET_IS_1 (!!(P4IN & BV(RESET_N)))
#define VREG_IS_1 (!!(P4IN & BV(VREG_EN)))
#define FIFOP_IS_1 (!!(P1IN & BV(FIFO_P)))
#define SFD_IS_1 (!!(P4IN & BV(SFD)))
/* The CC2420 reset pin. */
#define SET_RESET_INACTIVE() ( P4OUT |= BV(RESET_N) )
#define SET_RESET_ACTIVE() ( P4OUT &= ~BV(RESET_N) )
/* CC2420 voltage regulator enable pin. */
#define SET_VREG_ACTIVE() ( P4OUT |= BV(VREG_EN) )
#define SET_VREG_INACTIVE() ( P4OUT &= ~BV(VREG_EN) )
/* CC2420 rising edge trigger for external interrupt 0 (FIFOP). */
#define FIFOP_INT_INIT() do {\
P1IES &= ~BV(FIFO_P);\
CLEAR_FIFOP_INT();\
} while (0)
/* FIFOP on external interrupt 0. */
#define ENABLE_FIFOP_INT() do { P1IE |= BV(FIFO_P); } while (0)
#define DISABLE_FIFOP_INT() do { P1IE &= ~BV(FIFO_P); } while (0)
#define CLEAR_FIFOP_INT() do { P1IFG &= ~BV(FIFO_P); } while (0)
/* Enables/disables CC2420 access to the SPI bus (not the bus).
*
* These guys should really be renamed but are compatible with the
* original Chipcon naming.
*
* SPI_CC2420_ENABLE/SPI_CC2420_DISABLE???
* CC2420_ENABLE_SPI/CC2420_DISABLE_SPI???
*/
#define SPI_ENABLE() ( P4OUT &= ~BV(CSN) ) /* ENABLE CSn (active low) */
#define SPI_DISABLE() ( P4OUT |= BV(CSN) ) /* DISABLE CSn (active low) */
/***********************************************************
FAST SPI: Low level functions
***********************************************************/
/* SPI input/output registers. */
#define SPI_TXBUF U0TXBUF
#define SPI_RXBUF U0RXBUF
/* USART0 Tx buffer ready? */
#define SPI_WAITFOREOTx() while ((U0TCTL & TXEPT) == 0)
/* USART0 Rx buffer ready? */
#define SPI_WAITFOREORx() while ((IFG1 & URXIFG0) == 0)
#define FASTSPI_TX(x)\
do {\
SPI_TXBUF = x;\
SPI_WAITFOREOTx();\
} while(0)
#define FASTSPI_RX(x)\
do {\
SPI_TXBUF = 0;\
SPI_WAITFOREORx();\
x = SPI_RXBUF;\
} while(0)
#define FASTSPI_RX_GARBAGE()\
do {\
SPI_TXBUF = 0;\
SPI_WAITFOREORx();\
SPI_RXBUF;\
} while(0)
#define FASTSPI_TX_MANY(p,c)\
do {\
for (UINT8 spiCnt = 0; spiCnt < (c); spiCnt++) {\
FASTSPI_TX(((BYTE*)(p))[spiCnt]);\
}\
} while(0)
#define FASTSPI_RX_WORD(x)\
do {\
SPI_TXBUF = 0;\
SPI_WAITFOREORx();\
x = SPI_RXBUF << 8;\
SPI_TXBUF = 0;\
SPI_WAITFOREORx();\
x |= SPI_RXBUF;\
} while (0)
#define FASTSPI_TX_ADDR(a)\
do {\
SPI_TXBUF = a;\
SPI_WAITFOREOTx();\
} while (0)
#define FASTSPI_RX_ADDR(a)\
do {\
SPI_TXBUF = (a) | 0x40;\
SPI_WAITFOREOTx();\
} while (0)
/***********************************************************
FAST SPI: Register access
***********************************************************/
// s = command strobe
// a = register address
// v = register value
#define FASTSPI_STROBE(s) \
do {\
SPI_ENABLE();\
FASTSPI_TX_ADDR(s);\
SPI_DISABLE();\
} while (0)
#define FASTSPI_SETREG(a,v)\
do {\
SPI_ENABLE();\
FASTSPI_TX_ADDR(a);\
FASTSPI_TX((BYTE) ((v) >> 8));\
FASTSPI_TX((BYTE) (v));\
SPI_DISABLE();\
} while (0)
#define FASTSPI_GETREG(a,v)\
do {\
SPI_ENABLE();\
FASTSPI_RX_ADDR(a);\
v= (BYTE)SPI_RXBUF;\
FASTSPI_RX_WORD(v);\
halWaitUs(1);\
SPI_DISABLE();\
} while (0)
// Updates the SPI status byte
#define FASTSPI_UPD_STATUS(s)\
do {\
SPI_ENABLE();\
SPI_TXBUF = CC2420_SNOP;\
SPI_WAITFOREOTx();\
s = SPI_RXBUF;\
SPI_DISABLE();\
} while (0)
/***********************************************************
FAST SPI: FIFO Access
***********************************************************/
// p = pointer to the byte array to be read/written
// c = the number of bytes to read/write
// b = single data byte
#define FASTSPI_WRITE_FIFO(p,c)\
do {\
UINT8 i;\
SPI_ENABLE();\
FASTSPI_TX_ADDR(CC2420_TXFIFO);\
for (i = 0; i < (c); i++) {\
FASTSPI_TX(((BYTE*)(p))[i]);\
}\
SPI_DISABLE();\
} while (0);
#define FASTSPI_WRITE_FIFO_NOCE(p,c)\
do {\
UINT8 i;\
FASTSPI_TX_ADDR(CC2420_TXFIFO);\
for (spiCnt = 0; spiCnt < (c); spiCnt++) {\
FASTSPI_TX(((BYTE*)(p))[spiCnt]);\
}\
} while (0)
#define FASTSPI_SELECT_RX_FIFO()\
SPI_ENABLE();\
FASTSPI_RX_ADDR(CC2420_RXFIFO);\
SPI_RXBUF;\
SPI_DISABLE();
//assumes the RX FIFO has already been selected!
#define FASTSPI_READ_FIFO_BYTE(b)\
SPI_ENABLE();\
FASTSPI_RX(b);\
halWaitUs(1);\
SPI_DISABLE();
//assumes FIFO RX has already been selected!
#define FASTSPI_READ_FIFO_NO_WAIT(p,c)\
do {\
UINT 8 spiCnt;\
SPI_ENABLE();\
for (spiCnt = 0; spiCnt < (c); spiCnt++) {\
FASTSPI_RX(((BYTE*)(p))[spiCnt]);\
}\
halWaitUs(1);\
SPI_DISABLE();\
} while (0)
//assumes FIFO RX has already been selected!
#define FASTSPI_READ_FIFO_GARBAGE(c)\
do {\
UINT 8 spiCnt;\
SPI_ENABLE();\
for (spiCnt = 0; spiCnt < (c); spiCnt++) {\
FASTSPI_RX_GARBAGE();\
}\
halWaitUs(1);\
SPI_DISABLE();\
} while (0)
/***********************************************************
FAST SPI: CC2420 RAM access (big or little-endian order)
***********************************************************/
// FAST SPI: CC2420 RAM access (big or little-endian order)
// p = pointer to the variable to be written
// a = the CC2420 RAM address
// c = the number of bytes to write
// n = counter variable which is used in for/while loops (UINT8)
//
// Example of usage:
// UINT8 n;
// UINT16 shortAddress = 0xBEEF;
// FASTSPI_WRITE_RAM_LE(&shortAddress, CC2420RAM_SHORTADDR, 2);
#define FASTSPI_WRITE_RAM_LE(p,a,c,n)\
do {\
SPI_ENABLE();\
FASTSPI_TX(0x80 | (a & 0x7F));\
FASTSPI_TX((a >> 1) & 0xC0);\
for (n = 0; n < (c); n++) {\
FASTSPI_TX(((BYTE*)(p))[n]);\
}\
SPI_DISABLE();\
} while (0)
#endif
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