8051-c.ini

* "Copyright (c) 2006 Robert B. Reese ("AUTHOR")" * All rights reserved. * (R. Reese, reese@ece.

ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90C56]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-5FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90C58]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90L31]
MAKE = HYNIX
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90L32]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90L320]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90L51]
MAKE = HYNIX
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90L52]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90L54]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90L56]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-5FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90L58]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97C1051]
MAKE = HYNIX
INTRAM = 40
ROM = 0-03FF
INSTR = MCS-51
ARCH = 80C751

[GMS97C2051]
MAKE = HYNIX
INTRAM = 80
ROM = 0-07FF
INSTR = MCS-51
ARCH = 80C751

[GMS97C51]
MAKE = HYNIX
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97C51H]
MAKE = HYNIX
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97C52]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97C52H]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97C54]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97C54H]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97C56]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-5FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97C56H]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-5FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97C58]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97C58H]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97L1051]
MAKE = HYNIX
INTRAM = 40
ROM = 0-03FF
INSTR = MCS-51
ARCH = 80C751

[GMS97L2051]
MAKE = HYNIX
INTRAM = 80
ROM = 0-07FF
INSTR = MCS-51
ARCH = 80C751

[GMS97L51]
MAKE = HYNIX
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97L52]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97L54]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97L56]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-5FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS97L58]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS99C58]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[HMS91C7132]
MAKE = HYNIX
INTRAM = 100
XRAM = 0-FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# (RESTRCTED USE OF MOVX INST 92)
# The XRAM is enabled by default, but may be diasabled via sfr bit EXCON.0

[HMS91C7134]
MAKE = HYNIX
INTRAM = 100
XRAM = 0-FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# (RESTRICTED USE OF MOVX INST 92)
# The XRAM is enabled by default, but may be diasabled via sfr bit EXCON.0

[HMS91C8032]
MAKE = HYNIX
INTRAM = 100
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# this chip claims to have 1K data RAM. This is because lower internal memory is banked - we do not support.

[HMS91C8108]
MAKE = HYNIX
INTRAM = 100
ROM = 0-1FFF
INSTR = MCS-51
ARCH = 8051
# this chip can expand its internal RAM with paging, this is not yet supported.

[HMS91C8116]
MAKE = HYNIX
INTRAM = 100
ROM = 0-3FFF
INSTR = MCS-51
ARCH = 8051
# this chip can expand its internal RAM with paging, this is not yet supported.

[HMS91C8132]
MAKE = HYNIX
INTRAM = 100
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# this chip can expand its internal RAM with paging, this is not yet supported.

[HMS97C7132]
MAKE = HYNIX
INTRAM = 100
XRAM = 0-00FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# (RESTRICTED USE OF MOVX INSTR 92)
# XRAM is available by default, but can be disabled via EXCON sfr.

[HMS97C7134]
MAKE = HYNIX
INTRAM = 100
XRAM = 0-00FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# (RESTRICTED USE OF MOVX INSTR 92)
# XRAM is available by default, but can be disabled via EXCON sfr.

[HMS97C8032]
MAKE = HYNIX
INTRAM = 100
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# this chip claims to have 1K data RAM. This is because lower internal memory is banked - we do not support.

[HMS97C8132]
MAKE = HYNIX
INTRAM = 100
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# this chip can expand its internal RAM with paging, this is not yet supported.

[HT83C51FX]
MAKE = HONEYWELL
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IA8044]
MAKE = INNOVASIC
INTRAM = C0
OFFRAM = 0-FFFF
ROM = 0-FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IA80C152]
MAKE = INNOVASIC
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IA8344]
MAKE = INNOVASIC
INTRAM = C0
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IC80C31]
MAKE = ICSI
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IC80C32]
MAKE = ICSI
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IC80C51]
MAKE = ICSI
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IC80C52]
MAKE = ICSI
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IC80C54]
MAKE = ICSI
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IC80C58]
MAKE = ICSI
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IC80LV31]
MAKE = ICSI
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IC80LV32]
MAKE = ICSI
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IC80LV51]
MAKE = ICSI
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IC80LV52]
MAKE = ICSI
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IC89C51A]
MAKE = ICSI
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IC89C52A]
MAKE = ICSI
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IS80C31]
MAKE = ISSI
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IS80C32]
MAKE = ISSI
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IS80C51]
MAKE = ISSI
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IS80C52]
MAKE = ISSI
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IS80LV31]
MAKE = ISSI
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IS80LV32]
MAKE = ISSI
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IS80LV51]
MAKE = ISSI
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IS80LV52]
MAKE = ISSI
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IS89C52]
MAKE = ISSI
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[IS89E54]
MAKE = ICSI
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has AUXRAM at 0-01FF, disabled by default, enabled via SFR
# E series are flash parts

[IS89E58]
MAKE = ICSI
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has AUXRAM at 0-01FF, disabled by default, enabled via SFR
# E series are flash parts

[IS89E64]
MAKE = ICSI
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-EFFF,F000-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has AUXRAM at 0-01FF, disabled by default, enabled via SFR
# E series are flash parts, E64 has 2 blocks - may be erased independently

[KS152JB]
MAKE = KAWASAKI
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# do not write to PORT 0 if external memory is used

[LPC47N252]
MAKE = SMSC
INTRAM = 100
XRAM = 0-FF
ROM = 0-FFFF
INSTR = MCS-51
ARCH =  8051
# has MPAGE register which can be used during MOVX instruction

[LZ87010]
MAKE = SHARP
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 1000-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = enhanced MCS-51
ARCH = 8051
# has 2 added instructions mapped in the unused 0xA5 position (TRAP and MOVC@(DPTR++),A)

[M6759]
MAKE = ACER
INTRAM = 100
XRAM = 0-FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has 64k internal flash, also supports additional 64k ROM
# XRAM can be disabled via SFR

[M8051EWARP]
MAKE = MENTOR
INTRAM = 100
XRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51 + additional instructions
ARCH = 8051
# additional instructions are implimented in the unused A5 position
# Has SFR E0 which may be reloacated to another address. Default address is A2h.
# External SFRs (ESFRs) may be implimented. They can occupy any address between 80-FF,
# (directly addressable) that has not yet occupied.
# An ESFR may be bit addressable if they are in C0,C8 or D8.

[MAX7651]
MAKE = MAXIM
INTRAM = 100
OFFRAM = 0100-FFFF
ROM = 0-3FBF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# ROM area 3FC0-3FFF is reserved on-chip, Address range may be utilised only if EA is 1
# on-chip program memory is flash, divided into 2 blocks

[MAX7652]
MAKE = MAXIM
INTRAM = 100
OFFRAM = 0100-FFFF
ROM = 0-1FFF,2000-3FBF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# ROM area 3FC0-3FFF is reserved on-chip, Address range may be utilised only if EA is 1
# on-chip program memory is flash, divided into 2 blocks

[MSC1210Y2]
MAKE = TI
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 400-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# can partition code memory to increase data memory
# can reposition XRAM to 8000,8FFF to increase code memory
# also has boot flash from F800-FFFF

[MSC1210Y3]
MAKE = TI
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 400-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# can partition code memory to increase data memory
# can reposition XRAM to 8000,8FFF to increase code memory
# also has boot flash from F800-FFFF

[MSC1210Y4]
MAKE = TI
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 400-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# can partition code memory to increase data memory
# can reposition XRAM to 8000,8FFF to increase code memory
# also has boot flash from F800-FFF