8051-c.ini

* "Copyright (c) 2006 Robert B. Reese ("AUTHOR")" * All rights reserved. * (R. Reese, reese@ece.

BANKADR = 8000-FFFF
BANKTYPE = C
INSTR = CIP-51
ARCH = 8051
# SFR space can be paged, up to 256 pages.
# Bank0 (0-7FFF) can be mapped into 8000-FFFF, but this is not yet supported.
# We currently only support COBANK select (bank select for MOVC ops) for bank0.
# Note that in bank3, 1FC00-1FFFF is reserved.
# Also scratchpad memory at 20000-200FF.

[C8051F126]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 2000-FFFF
ROM = 0-FFFF
BANKS = 1,3
BANKADR = 8000-FFFF
BANKTYPE = C
INSTR = CIP-51
ARCH = 8051
# SFR space can be paged, up to 256 pages.
# Bank0 (0-7FFF) can be mapped into 8000-FFFF, but this is not yet supported.
# We currently only support COBANK select (bank select for MOVC ops) for bank0.
# Note that in bank3, 1FC00-1FFFF is reserved.
# Also scratchpad memory at 20000-200FF.

[C8051F127]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 2000-FFFF
ROM = 0-FFFF
BANKS = 1,3
BANKADR = 8000-FFFF
BANKTYPE = C
INSTR = CIP-51
ARCH = 8051
# SFR space can be paged, up to 256 pages.
# Bank0 (0-7FFF) can be mapped into 8000-FFFF, but this is not yet supported.
# We currently only support COBANK select (bank select for MOVC ops) for bank0.
# Note that in bank3, 1FC00-1FFFF is reserved.
# Also scratchpad memory at 20000-200FF.

[C8051F206]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-03FF
ROM = 0-1DFF,2000-207F
INSTR = CIP-51
ARCH = 8051
# 1k external data memory is repeated throughout 64k memory, CIP-51 is fully compatible with MCS-51

[C8051F220]
MAKE = CYGNAL
INTRAM = 100
ROM = 0-1DFF,2000-207F
INSTR = CIP-51
ARCH = 8051
# 1k external data memory is repeated throughout 64k memory, CIP-51 is fully compatible with MCS-51

[C8051F221]
MAKE = CYGNAL
INTRAM = 100
ROM = 0-1DFF,2000-207F
INSTR = CIP-51
ARCH = 8051
# 1k external data memory is repeated throughout 64k memory, CIP-51 is fully compatible with MCS-51

[C8051F226]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-03FF
ROM = 0-1DFF,2000-207F
INSTR = CIP-51
ARCH = 8051
# 1k external data memory is repeated throughout 64k memory, CIP-51 is fully compatible with MCS-51

[C8051F230]
MAKE = CYGNAL
INTRAM = 100
ROM = 0-1DFF,2000-207F
INSTR = CIP-51
ARCH = 8051
# 1k external data memory is repeated throughout 64k memory, CIP-51 is fully compatible with MCS-51

[C8051F231]
MAKE = CYGNAL
INTRAM = 100
ROM = 0-1DFF,2000-207F
INSTR = CIP-51
ARCH = 8051
# 1k external data memory is repeated throughout 64k memory, CIP-51 is fully compatible with MCS-51

[C8051F236]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-03FF
ROM = 0-1DFF,2000-207F
INSTR = CIP-51
ARCH = 8051
# 1k external data memory is repeated throughout 64k memory, CIP-51 is fully compatible with MCS-51

[C8051F300]
MAKE = CYGNAL
INTRAM = 100
ROM = 0-1DFF
INSTR = CIP-51
ARCH = 8051
# CIP-51 is fully compatible with MCS-51

[C8051F301]
MAKE = CYGNAL
INTRAM = 100
ROM = 0-1DFF
INSTR = CIP-51
ARCH = 8051
# CIP-51 is fully compatible with MCS-51

[C8051F302]
MAKE = CYGNAL
INTRAM = 100
ROM = 0-1DFF
INSTR = CIP-51
ARCH = 8051
# CIP-51 is fully compatible with MCS-51

[C8051F303]
MAKE = CYGNAL
INTRAM = 100
ROM = 0-1DFF
INSTR = CIP-51
ARCH = 8051
# CIP-51 is fully compatible with MCS-51

[C8051F310]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-3FF
ROM = 0-3DFF
INSTR = CIP-51
ARCH = 8051
# CIP-51 is fully compatible with MCS-51
# Not all of Port 3 is pinned out

[C8051F311]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-3FF
ROM = 0-3DFF
INSTR = CIP-51
ARCH = 8051
# CIP-51 is fully compatible with MCS-51
# Not all of Port 3 is pinned out

[C8051F320]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-3FF
ROM = 0-3DFF
INSTR = CIP-51
ARCH = 8051
# has USB FIFOs from 400-7FF

[C8051F321]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-3FF
ROM = 0-3DFF
INSTR = CIP-51
ARCH = 8051
# has USB FIFOs from 400-7FF

[C8051F330]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-1FF
ROM = 0-1DFF
INSTR = CIP-51
ARCH = 8051

[C8051F331]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-1FF
ROM = 0-1DFF
INSTR = CIP-51
ARCH = 8051

[C8051F350]
MAKE = CYGNAL
INTRAM = 100
XRAM =  0-1FF
ROM = 0-1DFF
INSTR = CIP-51
ARCH = 8051

[C8051F351]
MAKE = CYGNAL
INTRAM = 100
XRAM =  0-1FF
ROM = 0-1DFF
INSTR = CIP-51
ARCH = 8051

[C8051F352]
MAKE = CYGNAL
INTRAM = 100
XRAM =  0-1FF
ROM = 0-1DFF
INSTR = CIP-51
ARCH = 8051

[C8051F353]
MAKE = CYGNAL
INTRAM = 100
XRAM =  0-1FF
ROM = 0-1DFF
INSTR = CIP-51
ARCH = 8051

[C868_1R]
MAKE = INFINEON
INTRAM = 100
XRAM = FF00-FFFF
ROM = 0-1FFF
INSTR = MCS-51
ARCH = 8051
# has 4K of Boot/self test ROM also

[C868_1S]
MAKE = INFINEON
INTRAM = 100
XRAM = FF00-FFFF
ROM = 0-1FFF
INSTR = MCS-51
ARCH = 8051
# has 4K of Boot/self test ROM also

[CC1010]
MAKE = CHIPCON
INTRAM = 80
XRAM = 0-7FF
ROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# has additional instruction TRAP (A5) used for dubugging purposes.
# dual data pointer.

##hack for the CC2430-128, only provides 64K code
[CC2430]
MAKE = CHIPCON
INTRAM = 100
XRAM = E000-FEFF
ROM = 0-DEFF
INSTR = MCS-51
ARCH = 8051
# has additional instruction TRAP (A5) used for dubugging purposes.
# dual data pointer.

[COM20051]
MAKE = SMSC
INTRAM = 100
OFFRAM = 0-FFFE
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# chip has relocatable set of registers for ARCNET.
# user should define the symbol ARCNETADDRESS with the value of the start address of ARCNET registers
# if undefined, this will default to 0.
# WARNING: this definition does not load the ADDRESSDECODE register (@ 0xFFFF), user's code MUST do this also.
# The ARCNET register address range (in external data) MUST also be reserved by the user with command options.

[COM20051I]
MAKE = SMSC
INTRAM = 100
OFFRAM = 0-FFFE
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# chip has relocatable set of registers for ARCNET.
# user should define the symbol ARCNETADDRESS with the value of the start address of ARCNET registers
# if undefined, this will default to 0.
# WARNING: this definition does not load the ADDRESSDECODE register (@ 0xFFFF), user's code MUST do this also.
# The ARCNET register address range (in external data) MUST also be reserved by the user with command options.

[CMX850]
MAKE = CML
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# can bank program memory, but this banking scheme must be defined in user code.
# Can enter a mode where program can execute from XRAM.

[CY7C68013]
MAKE = CYPRESS
INTRAM = 100
XRAM = 0-1FFF,E000-E1FF
OFFRAM = 2000-DFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# RAM also exists from E200-FFF - USB regs and buffers

[DMC8031]
MAKE = DAEWOO
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[DMC8032]
MAKE = DAEWOO
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[DMC8051]
MAKE = DAEWOO
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[DMC8052]
MAKE = DAEWOO
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[DS2250T_32]
MAKE = DALLAS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# non-volatile RAM range code/data partionable by bootloader is 0-7FFF

[DS2250T_64]
MAKE = DALLAS
INTRAM = 80
XRAM = 8000-FFFF
OFFRAM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# non-volatile RAM range code/data partionable by bootloader is 0-7FFF
# note external data range

[DS2250T_8]
MAKE = DALLAS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# non-volatile RAM range code/data partionable by bootloader is 0-1FFF

[DS2250_32]
MAKE = DALLAS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# non-volatile RAM range code/data partionable by bootloader is 0-7FFF

[DS2250_64]
MAKE = DALLAS
INTRAM = 80
XRAM = 8000-FFFF
OFFRAM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# non-volatile RAM range code/data partionable by bootloader is 0-7FFF
# note external data range

[DS2250_8]
MAKE = DALLAS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# non-volatile RAM range code/data partionable by bootloader is 0-1FFF

[DS2251T_128]
MAKE = DALLAS
INTRAM = 80
XRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# data/program memory are separate 64k blocks, no external memory expansion available

[DS2251T_32]
MAKE = DALLAS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# non-volatile RAM range code/data partionable by bootloader is 0-7FFF
# data/program memory is partitioned in 32K block

[DS2251T_64]
MAKE = DALLAS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# non-volatile RAM range code/data partionable by bootloader is 0-FFFF

[DS2252T_128]
MAKE = DALLAS
INTRAM = 80
XRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# DS2252T disallows off-chip program memory

[DS2252T_32]
MAKE = DALLAS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-7FFF
INSTR = MCS-51
ARCH = 8051
# DS2252T disallows off-chip program memory
# OFFROM entires just provide boundaries for user to abide by
# non-volatile RAM range code/data partionable by bootloader is 0-7FFF

[DS2252T_64]
MAKE = DALLAS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# DS2252T disallows off-chip program memory
# OFFROM entires just provide boundaries for user to abide by
# non-volatile RAM range code/data partionable by bootloader is 0-FFFF

[DS5000FP]
MAKE = DALLAS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# non-volatile RAM range code/data partionable by bootloader is 0-1FFF
# 0-30h of program memory is vector RAM.

[DS5000T_32]
MAKE = DALLAS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# non-volatile RAM range code/data partionable by bootloader is 0-7FFF

[DS5000T_8]
MAKE = DALLAS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# non-volatile RAM range code/data partionable by bootloader is 0-1FFF

[DS5000_32]
MAKE = DALLAS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# non-volatile RAM range code/data partionable by bootloader is 0-7FFF

[DS5000_8]
MAKE = DALLAS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# non-volatile RAM range code/data partionable by bootloader is 0-1FFF

[DS5001FP]
MAKE = DALLAS
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# non-volatile RAM range code/data partionable by bootloader is 0-FFFF
# 0-30h of program memory is vector RAM

[DS5002FP]
MAKE = DALLAS
INTRAM = 80
XRAM = 0-FFFF
OFFRAM = 0-FFFF
ROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# 0-30h of program memory is vector RAM
# DS5002FP disallows off-chip program memory

[DS80C310]
MAKE = DALLAS
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# variable speed MOVX instruction

[DS80C320]
MAKE = DALLAS
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# variable speed MOVX instruction

[DS80C323]
MAKE = DALLAS
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# variable speed MOVX instruction

[DS80C390]
MAKE = DALLAS
INTRAM = 100
XRAM = 0-FFF
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51 + modified
ARCH = 80C517
# 22 bit prog/data conter (extended mem access up to 4MB!), has 512b CAN message centre
# note: this chip can PARTITION program/data from 0,FFF

[DS80C400]
MAKE = DALLAS
INTRAM = 100
XRAM = 0-23FF
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51 + modified
ARCH = 80C517
# has 4 data pointers, each can enable auto increment feature.
# has 3 modes of addressing data/program:
# 16-bit mode is supported (default)
# 24-bit paged is not supported as entire pages of 64k are swapped at once
# 24-bit contiguous is not supported
# the on-chip RAM can be mapped to a different address via SFR settings.
# also has 256 bytes of RAM for CAN registers from DB00-DBFF.

[DS83C520]
MAKE = DALLAS
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# variable speed MOVX instruction, ROMSIZE feature
# has 4 diff memory conditions, each with diff address ranges

[DS83C530]
MAKE = DALLAS
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# ROMSIZE feature
# has 4 diff memory conditions, each with diff address ranges

[DS87C520]
MAKE = DALLAS
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# variable speed MOVX instruction, ROMSIZE feature
# has 4 diff memory conditions, each with diff address ranges

[DS87C530]
MAKE = DALLAS
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# ROMSIZE feature
# has 4 diff memory conditions, each with diff address ranges

[DS87C550]
MAKE = DALLAS
INTRAM = 100
XRAM = 0-03FF
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# ROMSIZE feature

[DS89C420]
MAKE = DALLAS
INTRAM = 100
XRAM = 0-3FF
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# also has page mode, Programmable while in-application:
# program memory divided into 2 programmable flash banks(0-1FFF,2000-3FFF).

[FHG8051]
MAKE = FRAUNHOFER
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# synthesizeable microcontroller core

[FIPSOC]
MAKE = SIDSA
INTRAM = 100
XRAM = FF00-FFFF
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# Has 512 bytes of boot memory from address 0.
# Care must be taken when using HW probing area or PL Block,
# not to interfere with data in same address range. 

[GMS90C31]
MAKE = HYNIX
INTRAM = 80
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90C32]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90C320]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90C51]
MAKE = HYNIX
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90C52]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[GMS90C54]
MAKE = HYNIX
INTRAM = 100
OFFRAM = 0-FFFF