8051-c.ini

* "Copyright (c) 2006 Robert B. Reese ("AUTHOR")" * All rights reserved. * (R. Reese, reese@ece.

MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FC00-FFFF, this is enabled by XMAP bit.

[C505A_L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FC00-FFFF, this is enabled by XMAP bit.

[C505C_2R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FF00-FFFF, this is enabled by XMAP bit.

[C505CA_2R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FC00-FFFF, this is enabled by XMAP bit.

[C505CA_4E]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FC00-FFFF, this is enabled by XMAP bit.

[C505CA_4R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FC00-FFFF, this is enabled by XMAP bit.

[C505CA_L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FC00-FFFF, this is enabled by XMAP bit.

[C505C_L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FF00-FFFF, this is enabled by XMAP bit.

[C505L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FF00-FFFF, this is enabled by XMAP bit.

[C505_L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FF00-FFFF, this is enabled by XMAP bit.

[C508_4E]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FC00-FFFF, this is enabled by XMAP bit.

[C508_4R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FC00-FFFF, this is enabled by XMAP bit.

[C509_L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 80C517
# has XRAM positioned at F400-FFFF, this is enabled by XMAP bit.
# has boot ROM from 0-1FF.
# has 4 diff modes, each has diff memory ranges.

[C511A_R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[C511_R]
MAKE = INFINEON
INTRAM = 80
OFFRAM = 0-FFFF
ROM = 0-9FF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[C513_1R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[C513A_2R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FF00-FFFF, this is enabled by XMAP bit.

[C513A_H]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-2FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FF00-FFFF, this is enabled by XMAP bit.

[C513A_L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FF00-FFFF, this is enabled by XMAP bit.

[C513AO_2E]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FF00-FFFF, this is enabled by XMAP bit.

[C513AO_2R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-3FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FF00-FFFF, this is enabled by XMAP bit.

[C513AO_L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FF00-FFFF, this is enabled by XMAP bit.

[C513A_R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-2FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FF00-FFFF, this is enabled by XMAP bit.

[C515_1R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[C515A_4R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FC00-FFFF, this is enabled by XMAP bit.

[C515A_L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# has XRAM positioned at FC00-FFFF, this is enabled by XMAP bit.

[C515C_8E]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# external memory may be used as an alternative to on chip memory.
# 2K XRAM (F800-FFFF) and 256b CAN-registers (F700-F7FF) are on-chip,
# but disabled by default.

[C515C_8R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# external memory may be used as an alternative to on chip memory.
# 2K XRAM (F800-FFFF) and 256b CAN-registers (F700-F7FF) are on-chip,
# but disabled by default.

[C515C_L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051
# 2K XRAM (F800-FFFF) and 256b CAN-registers (F700-F7FF) are on-chip,
# but disabled by default.

[C515_L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[C517A_4R]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-7FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 80C517
# has XRAM positioned at F800-FFFF, this is enabled by XMAP bit.

[C517A_L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 80C517
# has XRAM positioned at F800-FFFF, this is enabled by XMAP bit.

[C540U]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-0FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[C540U_L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[C541U]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[C541U_1E]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
ROM = 0-1FFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[C541U_L]
MAKE = INFINEON
INTRAM = 100
OFFRAM = 0-FFFF
OFFROM = 0-FFFF
INSTR = MCS-51
ARCH = 8051

[C8051F000]
MAKE = CYGNAL
INTRAM = 100
ROM = 0-7DFF,8000-807F
INSTR = CIP-51
ARCH = 8051
# the 2k external memory is repeated across 64k range, CIP-51 is fully compatible with MCS-51

[C8051F001]
MAKE = CYGNAL
INTRAM = 100
ROM = 0-7DFF,8000-807F
INSTR = CIP-51
ARCH = 8051
# the 2k external memory is repeated across 64k range, CIP-51 is fully compatible with MCS-51

[C8051F002]
MAKE = CYGNAL
INTRAM = 100
ROM = 0-7DFF,8000-807F
INSTR = CIP-51
ARCH = 8051
# the 2k external memory is repeated across 64k range, CIP-51 is fully compatible with MCS-51

[C8051F005]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-7FF
ROM = 0-7DFF,8000-807F
INSTR = CIP-51
ARCH = 8051
# the 2k external memory is repeated across 64k range, CIP-51 is fully compatible with MCS-51

[C8051F006]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-7FF
ROM = 0-7DFF,8000-807F
INSTR = CIP-51
ARCH = 8051
# the 2k external memory is repeated across 64k range, CIP-51 is fully compatible with MCS-51

[C8051F007]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-7FF
ROM = 0-7DFF,8000-807F
INSTR = CIP-51
ARCH = 8051
# the 2k external memory is repeated across 64k range, CIP-51 is fully compatible with MCS-51

[C8051F010]
MAKE = CYGNAL
INTRAM = 100
ROM = 0-7DFF,8000-807F
INSTR = CIP-51
ARCH = 8051
# the 2k external memory is repeated across 64k range, CIP-51 is fully compatible with MCS-51

[C8051F011]
MAKE = CYGNAL
INTRAM = 100
ROM = 0-7DFF,8000-807F
INSTR = CIP-51
ARCH = 8051
# the 2k external memory is repeated across 64k range, CIP-51 is fully compatible with MCS-51

[C8051F012]
MAKE = CYGNAL
INTRAM = 100
ROM = 0-7DFF,8000-807F
INSTR = CIP-51
ARCH = 8051
# the 2k external memory is repeated across 64k range, CIP-51 is fully compatible with MCS-51

[C8051F015]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-7FF
ROM = 0-7DFF,8000-807F
INSTR = CIP-51
ARCH = 8051
# the 2k external memory is repeated across 64k range, CIP-51 is fully compatible with MCS-51

[C8051F016]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-7FF
ROM = 0-7DFF,8000-807F
INSTR = CIP-51
ARCH = 8051
# the 2k external memory is repeated across 64k range, CIP-51 is fully compatible with MCS-51

[C8051F017]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-7FF
ROM = 0-7DFF,8000-807F
INSTR = CIP-51
ARCH = 8051
# the 2k external memory is repeated across 64k range, CIP-51 is fully compatible with MCS-51

[C8051F018]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-03FF
ROM = 0-3DFF,8000-807F
INSTR = CIP-51
ARCH = 8051
# The XRAM window is repeated accross entire memory range
# CIP-51 is fully compatible with MCS-51

[C8051F019]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-03FF
ROM = 0-3DFF,8000-807F
INSTR = CIP-51
ARCH = 8051
# The XRAM window is repeated accross entire memory range
# this device has PORTS 0-3, but only 0 & 1 are pinned out
# CIP-51 is fully compatible with MCS-51

[C8051F020]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 1000-FFFF
ROM = 0-FDFF
INSTR = CIP-51
ARCH = 8051
# CIP-51 is fully compatible with MCS-51

[C8051F021]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 1000-FFFF
ROM = 0-FDFF
INSTR = CIP-51
ARCH = 8051
# CIP-51 is fully compatible with MCS-51

[C8051F022]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 1000-FFFF
ROM = 0-FDFF
INSTR = CIP-51
ARCH = 8051
# CIP-51 is fully compatible with MCS-51

[C8051F023]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 1000-FFFF
ROM = 0-FDFF
INSTR = CIP-51
ARCH = 8051
# CIP-51 is fully compatible with MCS-51

[C8051F040]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 1000-FFFF
ROM = 0-FDFF
INSTR = CIP-51
ARCH = 8051
# An additional ammount of DATA flash is mapped in the program
# space at address 0x10000-0x10075, this is accessable if
# the ADFLSH bit in PSCTL SFR is set.
# CIP-51 is fully compatible with MCS-51

[C8051F041]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 1000-FFFF
ROM = 0-FDFF
INSTR = CIP-51
ARCH = 8051
# An additional ammount of DATA flash is mapped in the program
# space at address 0x10000-0x10075, this is accessable if
# the ADFLSH bit in PSCTL SFR is set.
# PORTS 4-7 are on chip but not pinned out.
# CIP-51 is fully compatible with MCS-51

[C8051F042]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 1000-FFFF
ROM = 0-FDFF
INSTR = CIP-51
ARCH = 8051
# An additional ammount of DATA flash is mapped in the program
# space at address 0x10000-0x10075, this is accessable if
# the ADFLSH bit in PSCTL SFR is set.
# CIP-51 is fully compatible with MCS-51

[C8051F043]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-0FFF
OFFRAM = 1000-FFFF
ROM = 0-FDFF
INSTR = CIP-51
ARCH = 8051
# An additional ammount of DATA flash is mapped in the program
# space at address 0x10000-0x10075, this is accessable if
# the ADFLSH bit in PSCTL SFR is set.
# PORTS 4-7 are on chip but not pinned out.
# CIP-51 is fully compatible with MCS-51

[C8051F060]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-0FFF
ROM = 0-FBFF
INSTR = CIP-51
ARCH = 8051
# An additional ammount of DATA flash is mapped in the program
# space at address 0x10000-0x10075, this is accessable if
# the ADFLSH bit in PSCTL SFR is set.
# PORTS 4-7 are on chip but not pinned out.
# CIP-51 is fully compatible with MCS-51


[C8051F061]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-0FFF
ROM = 0-FBFF
INSTR = CIP-51
ARCH = 8051
# An additional ammount of DATA flash is mapped in the program
# space at address 0x10000-0x10075, this is accessable if
# the ADFLSH bit in PSCTL SFR is set.
# PORTS 4-7 are on chip but not pinned out.
# CIP-51 is fully compatible with MCS-51


[C8051F062]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-0FFF
ROM = 0-FBFF
INSTR = CIP-51
ARCH = 8051
# An additional ammount of DATA flash is mapped in the program
# space at address 0x10000-0x10075, this is accessable if
# the ADFLSH bit in PSCTL SFR is set.
# PORTS 4-7 are on chip but not pinned out.
# CIP-51 is fully compatible with MCS-51


[C8051F063]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-0FFF
ROM = 0-FBFF
INSTR = CIP-51
ARCH = 8051
# An additional ammount of DATA flash is mapped in the program
# space at address 0x10000-0x10075, this is accessable if
# the ADFLSH bit in PSCTL SFR is set.
# PORTS 4-7 are on chip but not pinned out.
# CIP-51 is fully compatible with MCS-51


[C8051F120]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 2000-FFFF
ROM = 0-FFFF
BANKS = 1,3
BANKADR = 8000-FFFF
BANKTYPE = C
INSTR = CIP-51
ARCH = 8051
# SFR space can be paged, up to 256 pages.
# Bank0 (0-7FFF) can be mapped into 8000-FFFF, but this is not yet supported.
# We currently only support COBANK select (bank select for MOVC ops) for bank0.
# Note that in bank3, 1FC00-1FFFF is reserved.
# Also scratchpad memory at 20000-200FF.

[C8051F121]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 2000-FFFF
ROM = 0-FFFF
BANKS = 1,3
BANKADR = 8000-FFFF
BANKTYPE = C
INSTR = CIP-51
ARCH = 8051
# SFR space can be paged, up to 256 pages.
# Bank0 (0-7FFF) can be mapped into 8000-FFFF, but this is not yet supported.
# We currently only support COBANK select (bank select for MOVC ops) for bank0.
# Note that in bank3, 1FC00-1FFFF is reserved.
# Also scratchpad memory at 20000-200FF.

[C8051F122]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 2000-FFFF
ROM = 0-FFFF
BANKS = 1,3
BANKADR = 8000-FFFF
BANKTYPE = C
INSTR = CIP-51
ARCH = 8051
# SFR space can be paged, up to 256 pages.
# Bank0 (0-7FFF) can be mapped into 8000-FFFF, but this is not yet supported.
# We currently only support COBANK select (bank select for MOVC ops) for bank0.
# Note that in bank3, 1FC00-1FFFF is reserved.
# Also scratchpad memory at 20000-200FF.

[C8051F123]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 2000-FFFF
ROM = 0-FFFF
BANKS = 1,3
BANKADR = 8000-FFFF
BANKTYPE = C
INSTR = CIP-51
ARCH = 8051
# SFR space can be paged, up to 256 pages.
# Bank0 (0-7FFF) can be mapped into 8000-FFFF, but this is not yet supported.
# We currently only support COBANK select (bank select for MOVC ops) for bank0.
# Note that in bank3, 1FC00-1FFFF is reserved.
# Also scratchpad memory at 20000-200FF.

[C8051F124]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 2000-FFFF
ROM = 0-FFFF
BANKS = 1,3
BANKADR = 8000-FFFF
BANKTYPE = C
INSTR = CIP-51
ARCH = 8051
# SFR space can be paged, up to 256 pages.
# Bank0 (0-7FFF) can be mapped into 8000-FFFF, but this is not yet supported.
# We currently only support COBANK select (bank select for MOVC ops) for bank0.
# Note that in bank3, 1FC00-1FFFF is reserved.
# Also scratchpad memory at 20000-200FF.

[C8051F125]
MAKE = CYGNAL
INTRAM = 100
XRAM = 0-1FFF
OFFRAM = 2000-FFFF
ROM = 0-FFFF
BANKS = 1,3