📄 cntr_6m8.tdf
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--lpm_counter DEVICE_FAMILY="Stratix II" lpm_direction="UP" lpm_width=8 aclr clk_en clock q sclr
--VERSION_BEGIN 4.2 cbx_cycloneii 2004:08:25:19:39:42:SJ cbx_lpm_add_sub 2004:10:25:10:56:48:SJ cbx_lpm_compare 2004:10:18:11:29:46:SJ cbx_lpm_counter 2004:10:25:23:03:40:SJ cbx_lpm_decode 2004:08:15:21:16:20:SJ cbx_mgl 2004:10:26:10:32:18:SJ cbx_stratix 2004:09:23:18:28:34:SJ cbx_stratixii 2004:08:10:15:01:36:SJ VERSION_END
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related netlist (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only
-- to program PLD devices (but not masked PLD devices) from Altera. Any
-- other use of such megafunction design, netlist, support information,
-- device programming or simulation file, or any other related documentation
-- or information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to the
-- intellectual property, including patents, copyrights, trademarks, trade
-- secrets, or maskworks, embodied in any such megafunction design, netlist,
-- support information, device programming or simulation file, or any other
-- related documentation or information provided by Altera or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.
FUNCTION stratixii_lcell_comb (cin, dataa, datab, datac, datad, datae, dataf, datag, sharein)
WITH ( EXTENDED_LUT, LUT_MASK, SHARED_ARITH)
RETURNS ( combout, cout, shareout, sumout);
FUNCTION stratixii_lcell_ff (aclr, adatasdata, aload, clk, datain, ena, sclr, sload)
RETURNS ( regout);
--synthesis_resources = lut 8 reg 8
SUBDESIGN cntr_6m8
(
aclr : input;
clk_en : input;
clock : input;
q[7..0] : output;
sclr : input;
)
VARIABLE
counter_comb_bita0 : stratixii_lcell_comb
WITH (
EXTENDED_LUT = "OFF",
LUT_MASK = "000000000000AAAA",
SHARED_ARITH = "OFF"
);
counter_comb_bita1 : stratixii_lcell_comb
WITH (
EXTENDED_LUT = "OFF",
LUT_MASK = "0000555500003333",
SHARED_ARITH = "OFF"
);
counter_comb_bita2 : stratixii_lcell_comb
WITH (
EXTENDED_LUT = "OFF",
LUT_MASK = "0000555500003333",
SHARED_ARITH = "OFF"
);
counter_comb_bita3 : stratixii_lcell_comb
WITH (
EXTENDED_LUT = "OFF",
LUT_MASK = "0000555500003333",
SHARED_ARITH = "OFF"
);
counter_comb_bita4 : stratixii_lcell_comb
WITH (
EXTENDED_LUT = "OFF",
LUT_MASK = "0000555500003333",
SHARED_ARITH = "OFF"
);
counter_comb_bita5 : stratixii_lcell_comb
WITH (
EXTENDED_LUT = "OFF",
LUT_MASK = "0000555500003333",
SHARED_ARITH = "OFF"
);
counter_comb_bita6 : stratixii_lcell_comb
WITH (
EXTENDED_LUT = "OFF",
LUT_MASK = "0000555500003333",
SHARED_ARITH = "OFF"
);
counter_comb_bita7 : stratixii_lcell_comb
WITH (
EXTENDED_LUT = "OFF",
LUT_MASK = "0000555500003333",
SHARED_ARITH = "OFF"
);
counter_reg_bit1a[7..0] : stratixii_lcell_ff;
a_val[7..0] : WIRE;
aclr_actual : WIRE;
cnt_en : NODE;
data[7..0] : NODE;
external_cin : WIRE;
lsb_cin : WIRE;
ones[31..0] : WIRE;
s_val[7..0] : WIRE;
safe_q[7..0] : WIRE;
sload : NODE;
sset : NODE;
time_to_clear : WIRE;
updown_dir : WIRE;
updown_lsb : WIRE;
updown_other_bits : WIRE;
BEGIN
counter_comb_bita[0].cin = lsb_cin;
counter_comb_bita[1].cin = counter_comb_bita[0].cout;
counter_comb_bita[2].cin = counter_comb_bita[1].cout;
counter_comb_bita[3].cin = counter_comb_bita[2].cout;
counter_comb_bita[4].cin = counter_comb_bita[3].cout;
counter_comb_bita[5].cin = counter_comb_bita[4].cout;
counter_comb_bita[6].cin = counter_comb_bita[5].cout;
counter_comb_bita[7].cin = counter_comb_bita[6].cout;
counter_comb_bita[0].dataa = counter_reg_bit1a[0].regout;
counter_comb_bita[1].dataa = counter_reg_bit1a[1].regout;
counter_comb_bita[2].dataa = counter_reg_bit1a[2].regout;
counter_comb_bita[3].dataa = counter_reg_bit1a[3].regout;
counter_comb_bita[4].dataa = counter_reg_bit1a[4].regout;
counter_comb_bita[5].dataa = counter_reg_bit1a[5].regout;
counter_comb_bita[6].dataa = counter_reg_bit1a[6].regout;
counter_comb_bita[7].dataa = counter_reg_bit1a[7].regout;
counter_comb_bita[0].datab = updown_lsb;
counter_comb_bita[1].datab = updown_other_bits;
counter_comb_bita[2].datab = updown_other_bits;
counter_comb_bita[3].datab = updown_other_bits;
counter_comb_bita[4].datab = updown_other_bits;
counter_comb_bita[5].datab = updown_other_bits;
counter_comb_bita[6].datab = updown_other_bits;
counter_comb_bita[7].datab = updown_other_bits;
counter_reg_bit1a[].aclr = aclr_actual;
counter_reg_bit1a[].adatasdata = ((sset & s_val[]) # ((! sset) & data[]));
counter_reg_bit1a[].clk = clock;
counter_reg_bit1a[0].datain = counter_comb_bita[0].sumout;
counter_reg_bit1a[1].datain = counter_comb_bita[1].sumout;
counter_reg_bit1a[2].datain = counter_comb_bita[2].sumout;
counter_reg_bit1a[3].datain = counter_comb_bita[3].sumout;
counter_reg_bit1a[4].datain = counter_comb_bita[4].sumout;
counter_reg_bit1a[5].datain = counter_comb_bita[5].sumout;
counter_reg_bit1a[6].datain = counter_comb_bita[6].sumout;
counter_reg_bit1a[7].datain = counter_comb_bita[7].sumout;
counter_reg_bit1a[].ena = (clk_en & (((cnt_en # sclr) # sset) # sload));
counter_reg_bit1a[].sclr = sclr;
counter_reg_bit1a[].sload = (sset # sload);
a_val[] = ( ones[7..0]);
aclr_actual = aclr;
cnt_en = VCC;
data[] = GND;
external_cin = B"1";
lsb_cin = B"0";
ones[] = B"11111111111111111111111111111111";
q[] = safe_q[];
s_val[] = ( ones[7..0]);
safe_q[] = counter_reg_bit1a[].regout;
sload = GND;
sset = GND;
time_to_clear = B"0";
updown_dir = B"1";
updown_lsb = updown_dir;
updown_other_bits = ((! external_cin) # updown_dir);
END;
--VALID FILE
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