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📄 ga622t.h

📁 It is something about net security also.Maybe useful.Hope you like it.
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 */#define	TXDP_MASK		0xFFFFFFFC	/* Mask for Transmit Descriptor Pointer	*/#define	TXDP_HI_MASK	0xFFFFFFFF	/* Mask for Transmit Descriptor High word 										pointer *//*  * TXCFG - Transmit Configuration Register *//*	Max DMA burst size per Tx/Rx DMA burst	*/#define	MXDMA8			0x00100000	/* 8 bytes	*/#define	MXDMA16			0x00200000	/* 16 bytes	*/#define	MXDMA32			0x00300000	/* 32 bytes	*/#define	MXDMA64			0x00400000	/* 64 bytes	*/#define	MXDMA128		0x00500000	/* 128 bytes	*/#define	MXDMA256		0x00600000	/* 256 bytes	*/#define	MXDMA512		0x00700000	/* 512 bytes	*/#define	MXDMA1024		0x00000000	/* 1024 bytes	*/#define	ATP				0x10000000	/*	Automatic Transmit Padding	*/#define	HBI				0x40000000	/*	Heart Beat Ignore	*/#define	CSI				0x80000000	/*	Carrier Sense Ignore	*///Madhu #define	ECRETRY			0x00800000  /* Excessive collission retry enable */#define BRST_DIS        0x00080000  /* Excessive collission retry enable *//*  * RXCFG - Receive Configuration Register */#define	ALP				0x08000000#define	RX_FD			0x10000000#define	STRIPCRC		0x20000000#define	ARP				0x40000000#define AEP				0x80000000#define AIRL			0x04000000/* *	PQCR	- Priority Queueing Control Register. */#define	TXPQEN			0x00000001#define	RXPQ2			0x00000004#define	RXPQ3			0x00000008#define	RXPQ4			0x0000000c/* *	Wake Command / Status Register.  */#define	WKPHY			0x00000001#define	WKUCP			0x00000002#define	WKMCP			0x00000004#define	WKBCP			0x00000008#define	WKARP			0x00000010#define	WKPAT0			0x00000020#define	WKPAT1			0x00000040#define	WKPAT2			0x00000080#define	WKPAT3			0x00000100#define	WKMAG			0x00000200#define	MPSOE			0x00000400#define	PHYINT			0x00400000#define PATM0			0x08000000#define PATM1			0x10000000#define PATM2			0x20000000#define PATM3			0x40000000#define MPR				0x80000000/* *	PCR - Pause Control / Status Register. */#define	PS_FFLO_2K		0x00040000#define	PS_FFLO_4K		0x00080000#define	PS_FFLO_8K		0x000C0000#define	PS_FFHI_2K		0x00100000#define	PS_FFHI_4K		0x00200000#define	PS_FFHI_8K		0x00300000#define	PS_STLO_2		0x00400000#define	PS_STLO_4		0x00800000#define	PS_STLO_8		0x00C00000#define	PS_STHI_2		0x01000000#define	PS_STHI_4		0x02000000#define	PS_STHI_8		0x03000000#define	PLEN_SEL		0x00010000#define PSEN			0x80000000#define PS_MCAST		0x40000000//Madhu: Clean up#define PS_DA			0x20000000#define PS_RCVD			0x08000000//Ramit : Since PS_RCVD cannot be read back use PS_ACT#define PS_ACT			0x10000000/* *	Receive Filter / Match Control Register. */#define APAT0			0x00800000#define APAT1			0x01000000#define APAT2			0x02000000#define APAT3			0x04000000#define RFEN			0x80000000/* *	MIBC - Management Information Base Control Register. */#define MIBS			0x00000008#define	ACLR			0x00000004#define FRZ				0x00000002/* *	RFCR - Receive Flow/Filter Control Register */#define RFAA_shift      28#define RFEP_shift      16#define RFEN            0x80000000  /* RF enable */#define AAB           	0x40000000    /* RF accept all broadcasts */#define AAM           	0x20000000    /* RF accept all multicasts */#define AAU           	0x10000000    /* RF accept all unicast */#define APM             0x08000000  /* accept on perfect match */#define APAT            0x07800000  /* (&) accept on pattern match--bits 26-23 */#define AARP            0x00400000      /* accept ARP packets */#define MHEN            0x00200000      /* mulitcast hash enable */#define UHEN            0x00100000      /* unicast hash enable */#define ULM             0x00080000      /* U/L bit mask *//* *      VTCR - VLAN/IP Transmit Control Register */#define PPCHK   		0x00000008#define GCHK   			0x00000004#define VPPTI   		0x00000002#define VGTI   			0x00000001/* *      VRCR - VLAN/IP Receive Control Register */#define RUDPE  			0x00000080#define RTCPE  			0x00000040#define RIPE  			0x00000020#define IPEN   			0x00000010/* *	GIG - PHY Register (DP83891) definitions. */#define BMCR			0x00#define	BMSR			0x01#define	PHYIDR1			0x02#define	PHYIDR2			0x03#define	ANAR			0x04#define	ANLPAR			0x05#define	ANER			0x06#define	ANNPTR			0x07#define	ANNPRR			0x08#define	KTCR			0x09#define	KSTSR			0x0A#define STROP			0x10/*	0x0B - 0x0E	Reserved	*/#define	KSCR			0x0F#define	PHYSUP			0x11#define ECR1			0x10#define	TBTOR			0x12/* * BMCR - Basic Mode Control Register */#define	NCBIT			0x0400/* * BMCR - Basic Mode Control Register */#define	BMCR_RESET		0x8000#define	AUTONEGENABLE	0x1000#define	RESTARTAUTONEG	0x0200/* * BMSR - bit defintions */#define	AUTONEG_COMPLETE	0x0020//Ramit#define LINK_STATUS_UP		0x0004/* * KTCR bit definitions. */#define A1000BASETHD    0x00000100  /* Advertise 1000BASE-T Half duplex */#define A1000BASETFD    0x00000200  /* Advertise 1000BASE-T Full duplex *//* * ANAR - bit definitions. */#define NP				0x8000#define PAUSE 			0x0400#define A10BASETHD      0x00000020  /* 10BASE-TX Half Duplex Support */#define A10BASETFD      0x00000040  /* 10BASE-TX Full Duplex Support */#define A100BASETHD     0x00000080  /* 100BASE-TX Half Duplex Support */#define A100BASETFD     0x00000100  /* 100BASE-TX Full Duplex Support */#define T4              0x00000200  /* 100BASE-T4 Support   *//*  *	ANER Settings  */#define PAGE_RX			0x0002#define LP_NP_ABLE 		0x0008/*  *	Speed settings  */#define BMCR1000		0x0040#define BMCR100			0x2000#define BMCR10			0x0000#define	PHY_SPEED_MASK  0x0018#define	PHY_SPEED_10	0x0000#define	PHY_SPEED_100	0x0008#define	PHY_SPEED_1000	0x0010#define	PHY_DUPLEX_MASK 0x0002#define	PHY_LINK_UP		0x0004#ifdef PM_WOL/* Configuration command status register ( CFGCS ) */#define IOSEN			0x00000001#define MWIEN			0x00000010#define SERREN			0x00000100#define NCPEN 			0x00100000#define PM_D3C 			0x80000000#define PM_D3H 			0x40000000#define PM_D2 			0x20000000#define PM_D1 			0x10000000#define PM_D0 			0x08000000#endif/*** Define Macros ***//*** Typedef Definitions ***//*** Global (extern) Data Declarations ***//*** Global (extern)Functions Declaration ***/#endif 

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