hsm.c

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		if (pAdapter->RxSTLO > pAdapter->RxSTHI)
			pAdapter->RxSTLO = pAdapter->RxSTHI;
		
        if (pAdapter->RxFFLO == 2)
			Pcr_val |= PS_FFLO_2K;
        if (pAdapter->RxFFLO == 4)
			Pcr_val |= PS_FFLO_4K;
        if (pAdapter->RxFFLO == 8)
			Pcr_val |= PS_FFLO_8K;

        if (pAdapter->RxFFHI == 2)
			Pcr_val |= PS_FFHI_2K;
        if (pAdapter->RxFFHI == 4)
			Pcr_val |= PS_FFHI_4K;
        if (pAdapter->RxFFHI == 8)
			Pcr_val |= PS_FFHI_8K;

        if (pAdapter->RxSTLO == 2)
			Pcr_val |= PS_STLO_2;
        if (pAdapter->RxSTLO == 4)
			Pcr_val |= PS_STLO_4;
        if (pAdapter->RxSTLO == 8)
			Pcr_val |= PS_STLO_8;

        if (pAdapter->RxSTHI == 2)
			Pcr_val |= PS_STHI_2;
        if (pAdapter->RxSTHI == 4)
			Pcr_val |= PS_STHI_4;
        if (pAdapter->RxSTHI == 8)
			Pcr_val |= PS_STHI_8;
#endif
        
		Pcr_val |= pAdapter->PauseCounterVal;
        Pcr_val |= (PSEN | PS_MCAST | PS_DA);
		
		/* Do not Pause Frames for Half Duplex mode */
		if ( !(pAdapter->DuplexMode) ) {
			Pcr_val = 0;
		}

        NsmRegWrite32(pAdapter->pNsmContext, (pAdapter->RegAddr + PCR), 
			Pcr_val);
/* 
 *      MIBC    - MIB Control/Status Register.
 *
 *      Clear all the counters in the MIBC register. 
 */
        NsmRegRead32(pAdapter->pNsmContext, (pAdapter->RegAddr + MIBC), 
			&Mibc_val);
        Mibc_val |= ACLR;
        Mibc_val &= ~(FRZ);
        NsmRegWrite32(pAdapter->pNsmContext, (pAdapter->RegAddr + MIBC), 
			Mibc_val);

/*
 *	Set the default bits (APM , AAB) in RFCR. 
 */
		HsmRxFilter(pAdapter, 0);

}       /*      end of HsmInitRegs()    */

#ifdef _GA622T_
/******************************************************************************
*f*
*   Name:               
*			HsmCreateMapValue
*
*   Description:        
*			Create the mapping value and store it in pAdpater->PriMapVal.
*
*   Parameters:     
*			pAdapter        - Pointer to the adapter context.
*
*   Return Value:   
*			NONE.
*
*f*
******************************************************************************/
VOID
HsmCreateMapValue(AdapterContext *pAdapter)
{ 
	USHORT  AdapterPQ, OsPQ;

	AdapterPQ = pAdapter->TxNumPrio;
	OsPQ = pAdapter->OsPrio;
        
	if (pAdapter->OsPrio < AdapterPQ)
		AdapterPQ = OsPQ;

	if (pAdapter->OsPrio == AdapterPQ)
		pAdapter->TxPriMapVal = PRI_QUOTIENT;
	else 
		pAdapter->TxPriMapVal = ( OsPQ * PRI_QUOTIENT / AdapterPQ );

	AdapterPQ = pAdapter->RxNumPrio;
	if (pAdapter->OsPrio < AdapterPQ)
		AdapterPQ = OsPQ;

	if (pAdapter->OsPrio == AdapterPQ)
		pAdapter->RxPriMapVal = PRI_QUOTIENT;
	else 
		pAdapter->RxPriMapVal = ( OsPQ * PRI_QUOTIENT / AdapterPQ );

}       /*      End of HsmCreateMapValue        */ 
#endif 

/*
 *      Functions related to ISR.
 */

/******************************************************************************
*f*
*       Name :
*			HsmIsr
*
*       Description     :
*			This routine is called from NSM interrupt service routine. 
*			HsmIsr determines the interrupt type by reading Interrupt Status
*			Register and handles them appropriately.
*    
*       Parameters :
*			pAdapter        - pointer to AdapterContext  
*    
*       Return Value :
*			INTR_CLAIMED   - If interrupt is claimed.
*			INTR_UNCLAIMED - if otherwise.
*    
*f*
******************************************************************************/
UCHAR
HsmIsr(AdapterContext *pAdapter)
{
	UINT interruptStatus = pAdapter->interruptStatus;
	UINT phyStatus = 0;
	UINT Cr_val = 0;
	UINT Pcr_valtx;
	UINT Pcr_val;
	UINT Pcr_valrx;
	UINT Ihr_val;
	UINT CallTxCompleted = 0;
	UCHAR status = INTR_UNCLAIMED;
	UCHAR Stat;
	UCHAR priIdx;
	HsmTCB *pTCB;
	volatile DevDesc *pTxDp;
	volatile DevDesc *CurrDesc;
	volatile DevDesc *DescBase;
	UINT	Reg_val=0;
	UINT	Bmsr_val;			
	UINT	Bmcr_val;
	UINT	i = 0, Tx = 0, Rx = 0;
	UINT	N_stat;		
	/* 
	 * First thing in the ISR, disable all interrupts from the adapter 
	 * by writing a 0 to the interrupt enable flag in the Interrupt 
	 * Enable Register. Read the interrupt from the ISR.
	 */

	HsmDisableInterrupts(pAdapter);

	if ( !(interruptStatus) ) {
		NsmRegRead32(pAdapter->pNsmContext, pAdapter->RegAddr + ISR, &interruptStatus );	
		pAdapter->interruptStatus = interruptStatus;
	}

	/* while ( interruptStatus ) */
	if ( interruptStatus ) {
		status = INTR_CLAIMED;
		pAdapter->interruptStatus = interruptStatus;
#ifdef NSCDEBUG
		NsmDbgMsg1("HsmIsr : Interrupt Status",interruptStatus);
#endif


		
/* 
 * 		If HsmClose forces NIC to generate software interrupt (SWI) 
 * 		or HsmReset forces NIC to a soft reset state (RST triggers 
 * 		TXRCMP event) then process the packets posted to the adapter 
 * 		for transmission.
 */
/*
 * 		Power management (indicating the idleness of the adapter) 
 *		can be handled in  HsmTxCompleted().
 *     		if (interruptStatus & TXIDLE)
 *     				pAdapter->TxEnableFlag = 1;
 */


		
		
		
/* 
 *		Check if there's a receive interrupt and handle the same 
 */
		/*Madhu Combining both HsmRxPackets*/
		if (interruptStatus & ( RXOK | RXERR | RXIDLE | RXORN | RXSOVR) ) {

#ifdef NSCDEBUG
			NsmDbgMsg("HsmIsr: Got Receive interrupt \n");  
			
			NsmRegRead32(pAdapter->pNsmContext, (pAdapter->RegAddr + PCR), 
				&Pcr_val);
			
			/*Ramit : Since th PS_RCVD reads back '0' we check PS_ACT also*/
			if(Pcr_val & PS_ACT )  {
				NsmDbgMsg1("HsmIsr : Pause frame received 0x%x\n", Pcr_val );
			} 
#endif
			HsmRxPackets (pAdapter);
			if ((pAdapter->CurrHoldOff) && (interruptStatus & RXOK))
			{
				/*Madhu Don't bring it back, if we still have IDLE*/
				if (!(interruptStatus & ( RXIDLE | RXORN | RXSOVR) )) {
					if (pAdapter->IntrHoldoff) {
						Ihr_val = 0;
						pAdapter->CurrHoldOff = 0;
						Ihr_val = pAdapter->IntrHoldoff | IHCTL;
						NsmRegWrite32(pAdapter->pNsmContext,(pAdapter->RegAddr + IHR), 
						Ihr_val);
					}
				}
			}

		}







		
/* 
 *		Check if there's a transmit interrupt and handle the same 
 */ 
		if (interruptStatus & (TXOK | TXERR) ) {
#ifdef NSCDEBUG
			NsmDbgMsg("HsmIsr: Got Transmit interrupt \n");  
#endif
			HsmTxCompleted (pAdapter);
		} 		/*	end of if (interruptStatus & (TXOK | TXERR) ) */






		
		

		if (interruptStatus & (SWI_INTR) ) { 

/*
 *	Reset the Adapter (setting RST bit in CR register) and wait till the reset
 *	is complete.
 */
		
		/*Ramit : Wait for TXD and RXD and then read the ISR
		If we have a RXOK and TXOK then we set a bit and call 
		TxCompleted and RxPackets after the ResetComplete
		Following which we check for any pending Tx packets and start
		the TXEngine.*/
        		i = 0;
				do {
           	   		  	NsmSleep(pAdapter->pNsmContext, 5);   
                		NsmRegRead32(pAdapter->pNsmContext, (pAdapter->RegAddr + CR), 
							&Cr_val);
        		} while ( (Cr_val & (RXE | TXE)) && ++i<100);
			
			
				/*Ramit : new Status*/
				NsmRegRead32(pAdapter->pNsmContext, pAdapter->RegAddr + ISR, &N_stat );	
				
				/*Ramit : check for the TXOK and RXOK*/
				if ( N_stat & (TXOK | TXERR) )
					Tx = 1;
				if ( N_stat & (RXOK | RXERR) )
					Rx = 1;
			pAdapter->interruptStatus &= (~(TX_QUEUES | 0x80 | TXOK | TXERR));
			pAdapter->interruptStatus &= (~(RX_QUEUES | 0x2 | RXOK | RXERR));
				/*Ramit : Include the reset status*/
			pAdapter->interruptStatus |= N_stat;
			interruptStatus = pAdapter->interruptStatus;

			if ( Rx == 1 )
			{
				HsmRxPackets (pAdapter);
			}

			if ( Tx == 1 ) 
			{
				HsmTxCompleted (pAdapter);
			}

				
			
			if (pAdapter->AdapterStatus & ADAPTER_RESETTING)
			{
        		NsmRegWrite32(pAdapter->pNsmContext, (pAdapter->RegAddr + CR), RST);

        		i = 0;
				do {
           	   		  	NsmSleep(pAdapter->pNsmContext, 5);   
                		NsmRegRead32(pAdapter->pNsmContext, (pAdapter->RegAddr + CR), 
							&Cr_val);
        		} while ( (Cr_val & RST) && ++i<400 ); 

/*
 * Reset the PHY register using BMCR
 */
#ifdef _FA31X_
        		NsmRegWrite16(pAdapter->pNsmContext,
						(pAdapter->RegAddr + BMCR), BMCR_RESET);
#else
        		WriteMiiReg(pAdapter, BMCR, BMCR_RESET);
#endif
/*
 *      Wait for the BMCR_RESET bit to clear, for reset complete.
 */
        		i = 0;
				do {

	        		NsmSleep(pAdapter->pNsmContext, 5 );
#ifdef _FA31X_
					NsmRegRead16(pAdapter->pNsmContext,
							(pAdapter->RegAddr + BMCR), &Bmcr_val);
#else
					Bmcr_val = ReadMiiReg(pAdapter, BMCR);
#endif
        		} while ( (Bmcr_val & BMCR_RESET) && ++i<800 ); 

				/* Ramit : Clear the statistics MIB counter */
        		HsmClearStatistics(pAdapter);

/* There is a potential problem here if the BMCR_RESET has not completed the download won't have any effect */ 
#ifdef FWARE_DOWNLOAD
if (pAdapter->FileHandle) {
	
	/* Ramit : Wait For the Phy to reset properly */
	NsmSleep(pAdapter->pNsmContext, 500 );
	
	HsmDownLoadFirmwareInit(pAdapter);

	Stat = NsmDownLoadFirmwareFromFileX(pAdapter);
	
	if( Stat == FAILURE ) {
	
		/* Event log */
		NsmDownLoadFailed(pAdapter);
		/*
		 * Reset the PHY register using BMCR incase of a DownloadFail
		 */
#ifdef _FA31X_
						NsmRegWrite16(pAdapter->pNsmContext,
								(pAdapter->RegAddr + BMCR), BMCR_RESET);
#else
						WriteMiiReg(pAdapter, BMCR, BMCR_RESET);
#endif
		/*
		 *      Wait for the BMCR_RESET bit to clear, for reset complete.
		 */
						i = 0;
						do {

							NsmSleep(pAdapter->pNsmContext, 5 );
#ifdef _FA31X_
							NsmRegRead16(pAdapter->pNsmContext,
									(pAdapter->RegAddr + BMCR), &Bmcr_val);
#else
							Bmcr_val = ReadMiiReg(pAdapter, BMCR);
#endif
						} while ( (Bmcr_val & BMCR_RESET) && ++i<800 ); 

	}
	
	else { /* if the download is successful */
		
		HsmStartFirmWareCode(pAdapter);
 
  		Stat = HsmVerifyDownLoad(pAdapter);

		if(Stat == FAILURE)
		{
			/* Event log */
			NsmDownLoadFailed(pAdapter);
		/*
		 * Reset the PHY register using BMCR incase of a DownloadFail
		 */
#ifdef _FA31X_
						NsmRegWrite16(pAdapter->pNsmContext,
								(pAdapter->RegAddr + BMCR), BMCR_RESET);
#else
						WriteMiiReg(pAdapter, BMCR, BMCR_RESET);
#endif
		/*
		 *      Wait for the BMCR_RESET bit to clear, for reset complete.
		 */
						i = 0;
						do {

							NsmSleep(pAdapter->pNsmContext, 5 );
#ifdef _FA31X_
							NsmRegRead16(pAdapter->pNsmContext,
									(pAdapter->RegAddr + BMCR), &Bmcr_val);
#else
							Bmcr_val = ReadMiiReg(pAdapter, BMCR);
#endif
						} while ( (Bmcr_val & BMCR_RESET) && ++i<800 ); 

		}
	}
}
#endif

				
/*
 *	Set the MAC address stored in pAdapter->CurrMacAddr and load the filter 
 *	memory with the multicast addresses stored in the Adapter context.
 */
				refresh_mca_tbl(pAdapter);
				HsmSetMacAddress(pAdapter, pAdapter->CurrMacAddr);
				
				pAdapter->AdapterStatus &= ~LINK_UP;
				NsmIndicateLinkStatus(pAdapter);
				
				HsmOpen(pAdapter);

				/*Status already indicated*/
				pAdapter->interruptStatus &= ~PHY;
				interruptStatus = pAdapter->interruptStatus;
			}

		}

							/* End of SWI_INTR*/





	
	
/* 
 *		Collect adapter's MIB statistics if one of the MIB counters has reached 
 *		its interrupt threshold.
 */
		if ( interruptStatus & MIB ) 
			ReadMIBCounters(pAdapter);









/* 
 *  	Handle phy inte