hsm.c

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	RxDp[2][DESCCNT] = MaxRxDescCnt_2;
	RxDp[3][DESCCNT] = MaxRxDescCnt_3;

	pAdapter->IntrHoldoff  = 1;

#elif _FA31X_
	TxDp[0][MINDESCCNT] = MinTxDescCnt_0;
	TxDp[0][DESCCNT] = MaxTxDescCnt_0;

	RxDp[0][MINDESCCNT] = MinRxDescCnt_0;
	RxDp[0][DESCCNT] = MaxRxDescCnt_0;
#endif
*/

	/*Ramit : Setting up the descriptors */
#ifdef _GA622T_

pAdapter->TxDp[0][0] = TXDP;
pAdapter->TxDp[0][1] = 0;
pAdapter->TxDp[0][2] = 0;
pAdapter->TxDp[0][3] = TXDP0_PRISEL;
pAdapter->TxDp[1][0] = TXDP1;
pAdapter->TxDp[1][1] = 0;
pAdapter->TxDp[1][2] = 0;
pAdapter->TxDp[1][3] = TXDP1_PRISEL;
pAdapter->TxDp[2][0] = TXDP2;
pAdapter->TxDp[2][1] = 0;
pAdapter->TxDp[2][2] = 0;
pAdapter->TxDp[2][3] = TXDP2_PRISEL;
pAdapter->TxDp[3][0] = TXDP3;
pAdapter->TxDp[3][1] = 0;
pAdapter->TxDp[3][2] = 0;
pAdapter->TxDp[3][3] = TXDP3_PRISEL;

pAdapter->RxDp[0][0] = RXDP;
pAdapter->RxDp[0][1] = 0;
pAdapter->RxDp[0][2] = 0;
pAdapter->RxDp[0][3] = RXDP0_PRISEL;
pAdapter->RxDp[1][0] = RXDP1;
pAdapter->RxDp[1][1] = 0;
pAdapter->RxDp[1][2] = 0;
pAdapter->RxDp[1][3] = RXDP1_PRISEL;
pAdapter->RxDp[2][0] = RXDP2;
pAdapter->RxDp[2][1] = 0;
pAdapter->RxDp[2][2] = 0;
pAdapter->RxDp[2][3] = RXDP2_PRISEL;
pAdapter->RxDp[3][0] = RXDP3;
pAdapter->RxDp[3][1] = 0;
pAdapter->RxDp[3][2] = 0;
pAdapter->RxDp[3][3] = RXDP3_PRISEL;

#elif _FA31X_

pAdapter->TxDp[0][0] = TXDP;
pAdapter->TxDp[0][1] = 0;
pAdapter->TxDp[0][2] = 0;
pAdapter->TxDp[0][3] = TXDP0_PRISEL;

pAdapter->RxDp[0][0] = RXDP;
pAdapter->RxDp[0][1] = 0;
pAdapter->RxDp[0][2] = 0;
pAdapter->RxDp[0][3] = RXDP0_PRISEL;

UINT phyConfigData[] = { 0x0005e000,
                         0x00044000,
                         0x00040000,
                         0x0005a000,
                         0x00058000 };

#endif

#ifdef _GA622T_
	for (i=0; i<MAX_PRI_QUEUE; i++) {
	
		pAdapter->TxDp[i][MINDESCCNT] = (pAdapter->TxQueueSz[i]/2);
		pAdapter->TxDp[i][DESCCNT] = pAdapter->TxQueueSz[i];
		pAdapter->RxDp[i][MINDESCCNT] = (pAdapter->RxQueueSz[i]/2);
		pAdapter->RxDp[i][DESCCNT] = pAdapter->RxQueueSz[i];
	
	}

	pAdapter->IntrHoldoff  = 1;

#elif _FA31X_
	pAdapter->TxDp[0][MINDESCCNT] = (pAdapter->TxQueueSz[0]/2);
	pAdapter->TxDp[0][DESCCNT] = pAdapter->TxQueueSz[0];

	pAdapter->RxDp[0][MINDESCCNT] = (pAdapter->RxQueueSz[0]/2);
	pAdapter->RxDp[0][DESCCNT] = pAdapter->RxQueueSz[0];
#endif

/* Jags: Adding Code for loading of EEPROM Registers */

	NsmRegRead32(pAdapter->pNsmContext,(pAdapter->RegAddr+PTSCR), &Ptscr_val);
	Ptscr_val |= EELOAD;
	NsmRegWrite32(pAdapter->pNsmContext, (pAdapter->RegAddr+PTSCR), Ptscr_val);
	
	i = 0;
	do {
		NsmSleep(pAdapter->pNsmContext, 10);    
		NsmRegRead32(pAdapter->pNsmContext, (pAdapter->RegAddr + PTSCR), &Ptscr_val);
	} while ((Ptscr_val & EELOAD)); 

	HsmGetMacAddress(pAdapter);
#ifdef NSCDEBUG
   NsmDbgMsg1("HsmInitContext: The factory MAC address is %x \n", pAdapter->PermMacAddr);
#endif
#ifdef _GA622T_
	pAdapter->PhysCapabilities  = 
		( VLAN_TAG_INSERTION_GEN_ON | TX_CHKSUM_OFFLOAD_ON_GEN | 
			SET_RX_CHKSUM_OFFLOAD_ON | JUMBO_FRAMES_ON | AUTO_NEG_ON | 
			SET_WOL_ON | BIG_ENDIAN );
#elif _FA31X_
	pAdapter->PhysCapabilities  = 
		( JUMBO_FRAMES_ON | AUTO_NEG_ON | SET_WOL_ON | BIG_ENDIAN );
#endif

/*
 *      Determine the number of priority queues to be created based on Adapter 
 *      supported PQ and operating system supported PQ.
 */
	AdapterPQ = MAXPRI_ADAPTER;

#ifdef _GA622T_
/*
 *      In FA31X priority queues are not supported.
 */
	if (pAdapter->OsPrio < AdapterPQ)
		AdapterPQ = pAdapter->OsPrio;   
#endif
        
	pAdapter->NumPrio = pAdapter->TxNumPrio = pAdapter->RxNumPrio = AdapterPQ;

	return;

}       /*      End of HsmInitContext() */

/******************************************************************************
*f*
*   Name:               
*                       HsmInitRegs
*
*   Description:        
*                       Initialize the following registers. This is called from HsmOpen().
*
*                       1. Command Register(CR)
*                       2. Configuration Register (CFG)
*                       3. Interrupt Mask Register (IMR)
*                       4. Interrupt Hold-off Register (IHR)
*                       5. Transmit Configuration Register (TXCFG)
*                       6. Receive Configuration Register (RXCFG)
*                       7. Priority Queue Control Register (PQCR)
*
*   Parameters:     
*                       pAdapter        - Pointer to the adapter context.
*
*   Return Value:   
*                       NONE.
*
*f*
******************************************************************************/
VOID
HsmInitRegs(AdapterContext *pAdapter) 
{
	UCHAR           priIdx, Mibc_val;
	UINT            Flag, TxFlth, TxDrth, RxDrth;
	UINT            Cr_val , Cfg_val , Imr_val;
	UINT            Pcr_val , Ihr_val , Txcfg_val , Rxcfg_val , Pqcr_val;
	UINT            Bmcr_val;

	Cr_val = Cfg_val = Imr_val =  0;
	Pcr_val = Ihr_val = Txcfg_val = Rxcfg_val = Pqcr_val = 0;
	Bmcr_val = 0;

#ifdef NSCDEBUG
	NsmDbgMsg("HsmInitRegs: Initializing the registers \n");
#endif
/*
 *      Set the physical capabilties of the adapter. 
 */
	HsmSetPhyCapabilities(pAdapter, pAdapter->PhysCapabilities, 1);
/*
 *      CFG Register Setting. 
 *
 *      Read the Speed and Duplex mode and store the values in Adapter context.
 *      Set BEM bit if BIG_ENDIAN is set in pAdapter->PhysCapabilities.
 *      Set EXSTS_EN if VLAN/CHKSUM offloading is set in 
 *		pAdapter->PhysCapabilities.
 */
	NsmRegRead32(pAdapter->pNsmContext, (pAdapter->RegAddr + CFG), &Cfg_val);

#ifdef _GA622T_
	if ((Cfg_val & SPEEDMASK) == SPEED10)
		pAdapter->MediaSpeed = 10;
	if ((Cfg_val & SPEEDMASK) == SPEED100)
		pAdapter->MediaSpeed = 100;
	if ((Cfg_val & SPEEDMASK) == SPEED1000)
		pAdapter->MediaSpeed = 1000;

	if ((Cfg_val & DUPSTS) == FULL_DUPLEX)
		pAdapter->DuplexMode = FULL_DUPLEX;
	else
		pAdapter->DuplexMode = HALF_DUPLEX;
#elif _FA31X_
	if (Cfg_val & SPEED100)
		pAdapter->MediaSpeed = 100;
	else
		pAdapter->MediaSpeed = 10;

	if (Cfg_val & FDUP)
		pAdapter->DuplexMode = FULL_DUPLEX;
	else
		pAdapter->DuplexMode = HALF_DUPLEX;
#endif
	if (pAdapter->PhysCapabilities & BIG_ENDIAN)
		Cfg_val |= BEM;

/*
 *      Set ED (Excessive Deferral) and PINT_CTL (Phy.Interrupt control).
 */
#ifdef _GA622T_
		/*Ramit : Enable 64 bit data transfer and increase internal clock speed
		Cfg_val |= (EXD | PINT_DUPSTS | PINT_LNKSTS | PINT_SPDSTS);*/
		Cfg_val |= (EXD | PINT_DUPSTS | PINT_LNKSTS | PINT_SPDSTS | DATA64_EN | TMRTEST);
#else
		Cfg_val |= (EXD);
#endif

		NsmRegWrite32(pAdapter->pNsmContext, (pAdapter->RegAddr+CFG), Cfg_val);
#ifdef _GA622T_
/*
 *      CR - Command Register
 *
 *      Enable the TXPRI and RXPRI bits in the Command Register(CR).
 */
		NsmRegRead32(pAdapter->pNsmContext, (pAdapter->RegAddr + CR), &Cr_val);
		Cr_val = 0;
		for (priIdx = 0; priIdx < pAdapter->NumPrio; priIdx++)
			Cr_val |= (pAdapter->RxDp[priIdx][PRIQSEL]) ; /* Madhu Enable only RX queues*/

		NsmRegWrite32(pAdapter->pNsmContext, (pAdapter->RegAddr + CR), Cr_val);
#endif 
/*
 *      IMR     - Interrupt Mask Register.
 *
 *      Enable the bits in the Interrupt Mask Register (IMR).
 */
		Imr_val = (RXOK | RXERR | RXORN |RXSOVR | RXIDLE | TXOK |  
			TXERR | TXURN | MIB | SWI_INTR | PME | PHY | 
			RTABT | RMABT | TXRCMP | RXRCMP); 
#ifdef _GA622T_
		for (priIdx = 0; priIdx < pAdapter->NumPrio; priIdx++) { 
			Imr_val |= ( 1 << (27+priIdx) );     /* Tx descriptor priority */
			Imr_val |= ( 1 << (23+priIdx) );     /* Rx descriptor priority */
		} 
#endif
		NsmRegWrite32(pAdapter->pNsmContext,(pAdapter->RegAddr+ IMR), Imr_val);

#ifdef _GA622T_
/*
 *      IHR     - Interrupt Hold-off Register.
 *
 *      Set the Interrupt-holdoff value in IHR.
 */
		if (pAdapter->IntrHoldoff) {
			/* NsmRegRead32(pAdapter->pNsmContext,(pAdapter->RegAddr + IHR), 
				&Ihr_val);*/
			Ihr_val = (pAdapter->IntrHoldoff | IHCTL);
			NsmRegWrite32(pAdapter->pNsmContext,(pAdapter->RegAddr + IHR), 
				Ihr_val);
		}
#endif
/*
 *      TXCFG - Transmit Configuration register. 
 *
 *      Set the TX drain threshold, Tx Fill threshold, Max DMA burst size , 
 *      Automatic Transmit Padding, Carrier Sense Ignore bits , 
 *      Heart Beat Ignore in TXCFG register
 */
		/*Madhu Ashwani's comments
		NsmRegRead32(pAdapter->pNsmContext,(pAdapter->RegAddr + TXCFG), 
			&Txcfg_val);*/
		Txcfg_val = 0;
		
		/*Madhu Make it tunable for performance checks*/
		TxFlth  = ( (pAdapter->TxFlth * pAdapter->CacheLineSize) / 32 ) << 8;
		TxFlth &= 0xFF00;
		if (TxFlth == 0)
			TxFlth = (pAdapter->CacheLineSize / 32);

        TxDrth = (pAdapter->CacheLineSize * pAdapter->TxDrth / 32);
		TxDrth &= 0xFF;
		
		/* Ramit : Tunable */
		/*TxDrth  = 0;*/
        /*TxDrth  = 128;*/
		/*Txcfg_val &= (0xFFFFFF00);*/

        if (TxDrth > TxFlth)
			TxDrth = TxFlth;
        
		if (TxDrth)
                Txcfg_val |= TxDrth;

        if (TxFlth) 
                Txcfg_val |= TxFlth;
        
        
        switch (pAdapter->CacheLineSize ) {
                case 8:
                        Txcfg_val |= MXDMA8;
                        break;
                case 16:
                        Txcfg_val |= MXDMA16;
                        break;
                case 32:
                        Txcfg_val |= MXDMA32;
                        break;
                case 64:
                        Txcfg_val |= MXDMA64;
                        break;
                case 128:
                        Txcfg_val |= MXDMA128;
                        break;
                case 256:
                        Txcfg_val |= MXDMA256;
                        break;
                case 512:
                        Txcfg_val |= MXDMA512;
                        break;
                case 1024:
                        Txcfg_val |= MXDMA1024;
                        break;
				default:
						Txcfg_val |= MXDMA1024;
						break;
        }               /*      end of switch(pAdapter->CacheLineSize)  */

		if (pAdapter->DuplexMode & FULL_DUPLEX)
			Txcfg_val |= ( HBI | CSI );
		/*Ramit : CSI only in FULL DUPLEX MODE */
		Txcfg_val |= (ATP | ECRETRY);

		NsmRegWrite32(pAdapter->pNsmContext, (pAdapter->RegAddr + TXCFG),
			Txcfg_val);

/*
 *      RXCFG - Receive Configuration register. 
 *
 *      Set the RX drain threshold, Max DMA burst size, Strip CRC, Rx Full 
 *      Duplex, Accept Errored packets , Accept Runt packets , Accept Long 
 *		Packets.
 */
		/*Madhu Ashwani's comments
		NsmRegRead32(pAdapter->pNsmContext, (pAdapter->RegAddr + RXCFG),
			&Rxcfg_val);*/
        /*Ramit : Tunable parameter */
		/*RxDrth  = 0;*/
		/*Rxcfg_val &= (~(0x3F));*/
		Rxcfg_val = 0;
        
        RxDrth = (pAdapter->CacheLineSize * pAdapter->RxDrth / 32);
		RxDrth &= 0xFF;
       
		if (RxDrth)
                Rxcfg_val |= RxDrth;

        switch (pAdapter->CacheLineSize) {
                case 8:
                        Rxcfg_val |= MXDMA8;
                        break;
                case 16:
                        Rxcfg_val |= MXDMA16;
                        break;
                case 32:
                        Rxcfg_val |= MXDMA32;
                        break;
                case 64:
                        Rxcfg_val |= MXDMA64;
                        break;
                case 128:
                        Rxcfg_val |= MXDMA128;
                        break;
                case 256:
                        Rxcfg_val |= MXDMA256;
                        break;
				case 512:
                        Rxcfg_val |= MXDMA512;
                        break;
				case 1024:
                        Rxcfg_val |= MXDMA1024;
                        break;
				default:
                        Rxcfg_val |= MXDMA1024;
                        break;
        }        /*      end of switch(pAdapter->CacheLineSize)  */

		if (pAdapter->PhysCapabilities & JUMBO_FRAMES_ON)
                Rxcfg_val |= (ALP);

#ifdef _GA622T_
		/*Madhu
		Ramit : Do not accept ERRORED and RUNT packets
        Rxcfg_val |= (AEP | ARP | STRIPCRC | RX_FD | AIRL);*/
        Rxcfg_val |= ( STRIPCRC | AIRL );
		/*Ramit : RX_FD only in FULL DUPLEX mode*/
		if (pAdapter->DuplexMode & FULL_DUPLEX)
        	Rxcfg_val |= RX_FD;
		
#elif _FA31X_
        Rxcfg_val |= (ARP);
#endif

		NsmRegWrite32(pAdapter->pNsmContext,(pAdapter->RegAddr + RXCFG),
			Rxcfg_val);

#ifdef _GA622T_
/*
 *      PQCR    - Priority Queue Control Register. 
 *
 *      Set TXPQEN and RXPQ.
 */
		NsmRegRead32(pAdapter->pNsmContext, (pAdapter->RegAddr + PQCR), 
			&Pqcr_val);

		//if (pAdapter->TxNumPrio > 1)
		Pqcr_val |= TXPQEN;
        
		if (pAdapter->RxNumPrio == 4)
			Pqcr_val |= RXPQ4;
		if (pAdapter->RxNumPrio == 3)
			Pqcr_val |= RXPQ3;
		if (pAdapter->RxNumPrio == 2)
			Pqcr_val |= RXPQ2;
        
		NsmRegWrite32(pAdapter->pNsmContext, (pAdapter->RegAddr + PQCR), 
			Pqcr_val);
#endif 

/*
 *      PCR - Pause Control Register. 
 *
 *      Set Rx stat FIFO HI threshold, RX stat FIFO LO threshold, Rx Data Fifo 
 *      Hi threshold, Rx Data FIFO Lo threshold, Pause Length select, Pause 
 *      Counter value.
 */

		Pcr_val = 0;
        
#ifdef _GA622T_

		/*Ramit : Tunable
		RxFFLO = 2;
		RxFFHI = 4;
		
		RxSTLO = 2;
		RxSTHI = 4;*/
	
		if (pAdapter->RxFFLO > pAdapter->RxFFHI)
			pAdapter->RxFFLO = pAdapter->RxFFHI;