ti_cc_spi.c

sources for 蜒2500 chipcon modem

//----------------------------------------------------------------------------
//  void TI_CC_SPISetup(void)
//
//  DESCRIPTION:
//  Configures the assigned interface to function as a SPI port and
//  initializes it.
//----------------------------------------------------------------------------
//  void TI_CC_SPIWriteReg(char addr, char value)
//
//  DESCRIPTION:
//  Writes "value" to a single configuration register at address "addr".
//----------------------------------------------------------------------------
//  void TI_CC_SPIWriteBurstReg(char addr, char *buffer, char count)
//
//  DESCRIPTION:
//  Writes values to multiple configuration registers, the first register being
//  at address "addr".  First data byte is at "buffer", and both addr and
//  buffer are incremented sequentially (within the CCxxxx and MSP430,
//  respectively) until "count" writes have been performed.
//----------------------------------------------------------------------------
//  char TI_CC_SPIReadReg(char addr)
//
//  DESCRIPTION:
//  Reads a single configuration register at address "addr" and returns the
//  value read.
//----------------------------------------------------------------------------
//  void TI_CC_SPIReadBurstReg(char addr, char *buffer, char count)
//
//  DESCRIPTION:
//  Reads multiple configuration registers, the first register being at address
//  "addr".  Values read are deposited sequentially starting at address
//  "buffer", until "count" registers have been read.
//----------------------------------------------------------------------------
//  char TI_CC_SPIReadStatus(char addr)
//
//  DESCRIPTION:
//  Special read function for reading status registers.  Reads status register
//  at register "addr" and returns the value read.
//----------------------------------------------------------------------------
//  void TI_CC_SPIStrobe(char strobe)
//
//  DESCRIPTION:
//  Special write function for writing to command strobe registers.  Writes
//  to the strobe at address "addr".
//----------------------------------------------------------------------------







void TI_CC_SPISetup(void)
{
    cs=1;
    sck=0;
    mosi=0;
}

// Output eight-bit value using selected bit-bang pins
void TI_CC_SPI_bitbang_out(char value)
{
  char x;

  for(x=8;x>0;x--){
    if(value & 0x80)mosi=1;                                    
    else mosi=0;
    #asm("nop")
    
    sck=1;
    value<<=1;
    #asm("nop")
    sck=0;
    #asm("nop")
    
    }
}

// Input eight-bit value using selected bit-bang pins
char TI_CC_SPI_bitbang_in()
{
  unsigned char x=0;
  unsigned char y;
        x=0;
  for(y=8;y>0;y--){
    sck=1;
    #asm("nop")
    x<<=1;
    if(miso==1){x|=0b00000001;} 
    sck=0;
    #asm("nop")
    
    }                                         // Store next bit
  return(x);

 


}

void TI_CC_SPIWriteReg(char addr, char value)
{
    cs=0;                                   // /CS enable
    while (miso);                           // Wait CCxxxx ready
    TI_CC_SPI_bitbang_out(addr);            // Send address
    TI_CC_SPI_bitbang_out(value);           // Send data
    cs=1;                                   // /CS disable
}

void TI_CC_SPIWriteBurstReg(char addr, char *buffer, char count)
{
    char i;

    cs=0;                                   // /CS enable
    while (miso);                           // Wait CCxxxx ready
    TI_CC_SPI_bitbang_out(addr | TI_CCxxx0_WRITE_BURST);   // Send address
    for (i = 0; i < count; i++)
      TI_CC_SPI_bitbang_out(buffer[i]);     // Send data
      cs=1;                                   // /CS disable
}

char TI_CC_SPIReadReg(char addr)
{
  char x;

  cs=0;
  while (miso);
  TI_CC_SPI_bitbang_out(addr | TI_CCxxx0_READ_SINGLE);//Send address
  x = TI_CC_SPI_bitbang_in();               // Read data
  cs=1;                                   // /CS disable
  return x;
}

void TI_CC_SPIReadBurstReg(char addr, char *buffer, char count)
{
  char i;
  cs=0;
  while (miso);
  TI_CC_SPI_bitbang_out(addr | TI_CCxxx0_READ_BURST);    // Send address
  for (i = 0; i < count; i++){
    buffer[i] = TI_CC_SPI_bitbang_in();// Read data
    }     
  cs=1;                                   // /CS disable
  }

char TI_CC_SPIReadStatus(char addr)
{
  char x;
  cs=0;
  while (miso);                           // Wait CCxxxx ready                                   // /CS enable
  TI_CC_SPI_bitbang_out(addr | TI_CCxxx0_READ_BURST);      // Send address
  x = TI_CC_SPI_bitbang_in();               // Read data
  cs=1;                                   // /CS disable
  return x;
}

void TI_CC_SPIStrobe(char strobe)
{
  cs=0;
  while (miso);                           // Wait CCxxxx ready                                   // /CS enable
  TI_CC_SPI_bitbang_out(strobe);            // Send strobe
  cs=1;                                   // /CS disable
}

void TI_CC_PowerupResetCCxxxx(void)
{
    cs=1;
    delay_us(40);
    cs=0;
    delay_us(40);
    cs=1;
    delay_us(45);
    cs=0;
    
    while(miso);
    TI_CC_SPI_bitbang_out(TI_CCxxx0_SRES);
    while(miso);
    cs=1;
    delay_ms(45);
     
}


// Chipcon
// Product = CC2500
// Chip version = E
// Crystal accuracy = 10 ppm
// X-tal frequency = 26 MHz
// RF output power = 0 dBm
// RX filterbandwidth = 551.067708 kHz
// Phase = 1
// Datarate = 250.240707 kbps
// Modulation = (7) MSK
// Manchester enable = (0) Manchester disabled
// RF Frequency = 2432.999988 MHz
// Channel spacing = 199.788952 kHz
// Channel number = 0
// Optimization = Sensitivity
// Sync mode = (3) 30/32 sync word bits detected
// Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
// CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
// Forward Error Correction = (0) FEC disabled
// Length configuration = (1) Variable length packets, packet length configured by the first received byte after sync word.
// Packetlength = 255
// Preamble count = (2)  4 bytes
// Append status = 1
// Address check = (0) No address check
// FIFO autoflush = 1
// Device address = 0
// GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet
// GDO2 signal selection = (11) Serial Clock
void writeRFSettings(void)
{
    // Write register settings

TI_CC_SPIWriteReg(TI_CCxxx0_FSCTRL1,0x0c);
TI_CC_SPIWriteReg(TI_CCxxx0_FSCTRL0,0x00);
TI_CC_SPIWriteReg(TI_CCxxx0_FREQ2,0x5B);
TI_CC_SPIWriteReg(TI_CCxxx0_FREQ1,0xFB);
TI_CC_SPIWriteReg(TI_CCxxx0_FREQ0,0x04);//04 rx    7c jeep
TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG4,0x2d);
TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG3,0x36);
TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG2,0x73);
TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG1,0xc2);
TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG0,0xEF);
TI_CC_SPIWriteReg(TI_CCxxx0_CHANNR,0x00);
TI_CC_SPIWriteReg(TI_CCxxx0_DEVIATN,0x01);
TI_CC_SPIWriteReg(TI_CCxxx0_FREND1,0x56);
TI_CC_SPIWriteReg(TI_CCxxx0_FREND0,0x10);
TI_CC_SPIWriteReg(TI_CCxxx0_MCSM2,0x07);
TI_CC_SPIWriteReg(TI_CCxxx0_MCSM1,0x3c);//30
TI_CC_SPIWriteReg(TI_CCxxx0_MCSM0,0x18);
TI_CC_SPIWriteReg(TI_CCxxx0_FOCCFG,0x15);
TI_CC_SPIWriteReg(TI_CCxxx0_BSCFG,0x6C);
TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL2,0xc3);
TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL1,0x00);
TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL0,0x91);
TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL3,0xea);
TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL2,0x0A);
TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL1,0x00);
TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL0,0x11);
TI_CC_SPIWriteReg(TI_CCxxx0_FSTEST,0x59);
TI_CC_SPIWriteReg(TI_CCxxx0_TEST2,0x8f);
TI_CC_SPIWriteReg(TI_CCxxx0_TEST1,0x21);
TI_CC_SPIWriteReg(TI_CCxxx0_TEST0,0x0B);
TI_CC_SPIWriteReg(TI_CCxxx0_IOCFG2,0x0F);
TI_CC_SPIWriteReg(TI_CCxxx0_IOCFG0,0x06);
TI_CC_SPIWriteReg(TI_CCxxx0_PKTCTRL1,0x0d);//05
TI_CC_SPIWriteReg(TI_CCxxx0_PKTCTRL0,0x05);
TI_CC_SPIWriteReg(TI_CCxxx0_ADDR,0x01);
TI_CC_SPIWriteReg(TI_CCxxx0_PKTLEN,0xff);
TI_CC_SPIWriteReg(TI_CCxxx0_FIFOTHR,0x07);

}


//-----------------------------------------------------------------------------
//  void RFSendPacket(char *txBuffer, char size)
//
//  DESCRIPTION:
//  This function transmits a packet with length up to 63 bytes.  To use this
//  function, GD00 must be configured to be asserted when sync word is sent and
//  de-asserted at the end of the packet, which is accomplished by setting the
//  IOCFG0 register to 0x06, per the CCxxxx datasheet.  GDO0 goes high at
//  packet start and returns low when complete.  The function polls GDO0 to
//  ensure packet completion before returning.
//
//  ARGUMENTS:
//      char *txBuffer
//          Pointer to a buffer containing the data to be transmitted
//
//      char size
//          The size of the txBuffer
//-----------------------------------------------------------------------------
void RFSendPacket(char *txBuffer, char size)
{
    TI_CC_SPIWriteBurstReg(TI_CCxxx0_TXFIFO, txBuffer, size); // Write TX data
    TI_CC_SPIStrobe(TI_CCxxx0_STX);         // Change state to TX, initiating
}

//-----------------------------------------------------------------------------
//  char RFReceivePacket(char *rxBuffer, char *length)
//
//  DESCRIPTION:
//  Receives a packet of variable length (first byte in the packet must be the
//  length byte).  The packet length should not exceed the RXFIFO size.  To use
//  this function, APPEND_STATUS in the PKTCTRL1 register must be enabled.  It
//  is assumed that the function is called after it is known that a packet has
//  been received; for example, in response to GDO0 going low when it is
//  configured to output packet reception status.
//
//  The RXBYTES register is first read to ensure there are bytes in the FIFO.
//  This is done because the GDO signal will go high even if the FIFO is flushed
//  due to address filtering, CRC filtering, or packet length filtering.
//
//  ARGUMENTS:
//      char *rxBuffer
//          Pointer to the buffer where the incoming data should be stored
//      char *length
//          Pointer to a variable containing the size of the buffer where the
//          incoming data should be stored. After this function returns, that
//          variable holds the packet length.
//
//  RETURN VALUE:
//      char
//          0x80:  CRC OK
//          0x00:  CRC NOT OK (or no pkt was put in the RXFIFO due to filtering)
//-----------------------------------------------------------------------------
char RFReceivePacket(char *rxBuffer, char *length)
{
  char status[2];
  char pktLen;
    
  
     
  if ((TI_CC_SPIReadStatus(TI_CCxxx0_RXBYTES) & TI_CCxxx0_NUM_RXBYTES))
  {
      
    pktLen = TI_CC_SPIReadReg(TI_CCxxx0_RXFIFO); // Read length byte
    if (pktLen <= *length)                  // If pktLen size <= rxBuffer
    {
      
      TI_CC_SPIReadBurstReg(TI_CCxxx0_RXFIFO, rxBuffer, pktLen); // Pull data
      *length = pktLen;                     // Return the actual size
      TI_CC_SPIReadBurstReg(TI_CCxxx0_RXFIFO, status, 2);
      LQI=status[1];
      RSSI=status[0];                                      // Read appended status bytes
      return (char)(status[TI_CCxxx0_LQI_RX]&TI_CCxxx0_CRC_OK);
    }                                       // Return CRC_OK bit
    else
    {
      
      *length = pktLen;                     // Return the large size
      TI_CC_SPIStrobe(TI_CCxxx0_SFRX);      // Flush RXFIFO
      return 0;                             // Error
    }
  }
  else{
      
      return 0;                             // Error
      }
}

//---------------------------------------------------------------------------------------------------------
void RF_TX_proc(void){ // 钺疣犷蜿