📄 tmhal.c
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/*----------------------------------------------------------------------------
COPYRIGHT (c) 1997 by Philips Semiconductors
THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY ONLY BE USED AND COPIED IN
ACCORDANCE WITH THE TERMS AND CONDITIONS OF SUCH A LICENSE AND WITH THE
INCLUSION OF THE THIS COPY RIGHT NOTICE. THIS SOFTWARE OR ANY OTHER COPIES
OF THIS SOFTWARE MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY OTHER
PERSON. THE OWNERSHIP AND TITLE OF THIS SOFTWARE IS NOT TRANSFERRED.
THE INFORMATION IN THIS SOFTWARE IS SUBJECT TO CHANGE WITHOUT ANY PRIOR NOTICE
AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY Philips Semiconductor.
PHILIPS ASSUMES NO RESPONSIBILITY FOR THE USE OR RELIABILITY OF THIS SOFTWARE
ON PLATFORMS OTHER THAN THE ONE ON WHICH THIS SOFTWARE IS FURNISHED.
----------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////
// HISTORY
//
// 960510 TR Created
// 979527 TR Ported to Windows NT with TMMan V4.0 interfaces
// 970806 Tilakraj Roy Ported to Windows NT with TMMan V5.0 interfaces
//
// Following SCCS macros added by Nadeem:
//
// Module name : tmhal.c 1.12
//
// Last update : 09:43:43 - 99/06/24
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
// SYSTEM INCLUDE FILES
//////////////////////////////////////////////////////////////////////////////
#define WANTVXDWRAPS
#include <basedef.h>
#include <vmm.h>
#include <vxdwraps.h>
#include <vpicd.h>
#include <configmg.h>
#pragma VxD_LOCKED_CODE_SEG
#pragma VxD_LOCKED_DATA_SEG
//////////////////////////////////////////////////////////////////////////////
// DRIVER SPECIFIC INCLUDE FILES
//////////////////////////////////////////////////////////////////////////////
#include "tmmanlib.h"
#include "platform.h"
#include "mmio.h"
//////////////////////////////////////////////////////////////////////////////
// MANIFEST CONSTANTS
//////////////////////////////////////////////////////////////////////////////
#define HalFourCC tmmanOBJECTID ( 'H', 'A', 'L', ' ' )
//////////////////////////////////////////////////////////////////////////////
// TYPEDEFS
//////////////////////////////////////////////////////////////////////////////
typedef struct tagHalObject
{
GenericObject Object;
ULONG TMDeviceVendorID;
ULONG TMSubsystemID;
ULONG TMClassRevisionID;
ULONG BridgeDeviceVendorID;
ULONG BridgeSubsystemID;
ULONG BridgeClassRevisionID;
UInt32 SelfInterrupt; // from Target -> Host
UInt32 PeerInterrupt; // Host -> Target
HalInterruptHandler Handler;
Pointer Context;
HalControl* Control;
/* true - target processor is running in different indianess */
/* false - target processor is running in different indianess */
Bool Swapping;
UInt32 PeerMajorVersion;
UInt32 PeerMinorVersion;
/* BEGIN Platform Specific */
ULONG BusNumber;
ULONG DeviceNumber;
ULONG FunctionNumber;
PHYSICAL_ADDRESS MMIOHostAddrPhysical;
PHYSICAL_ADDRESS MMIOAddrPhysical;
ULONG MMIOLength;
PUCHAR MMIOAddrKernel;
PHYSICAL_ADDRESS SDRAMHostAddrPhysical;
PHYSICAL_ADDRESS SDRAMAddrPhysical;
ULONG SDRAMLength;
PUCHAR SDRAMAddrKernel;
ULONG MappedInterruptVector;
BOOLEAN FirstTimeReset;
ULONG InterruptObject;
ULONG DPCObject;
UInt32 DSPNumber;
ULONG NumberOfMapRegisters;
ULONG SpeculativeLoadFix;
ULONG SDRAMMapCount;
ULONG PCIRegisters[constTMMANPCIRegisters];
UInt32 Offset;
} HalObject;
//////////////////////////////////////////////////////////////////////////////
// PROTOTYPES
//////////////////////////////////////////////////////////////////////////////
void halDumpObject (
UInt32 HalHandle );
VOID halUnmapUserAddress (
PVOID UserModeVirtualAddress );
PVOID halMapKernelAddressToUserAddress (
HANDLE PhysicalMemoryHandle,
PVOID KernelModeVirtualAddress,
ULONG Length );
BOOL halHardwareInterruptHandler(
ULONG VMHandle,
ULONG IRQHandle,
PVOID Context );
VOID halDeferredInterruptHandler (
ULONG VMHandle,
PVOID Context,
PVOID ClientRegister );
//////////////////////////////////////////////////////////////////////////////
// IMPLEMENTATION
//////////////////////////////////////////////////////////////////////////////
TMStatus halCreate (
Pointer Parameters,
UInt32* HalHandlePointer )
{
TMStatus Status = statusHalInitializationFail;
HalObject* Hal;
ULONG AddressSpace;
VID IRQDescriptors;
ULONG Idx;
if ( ( Hal = objectAllocate (
sizeof ( HalObject ),
HalFourCC ) ) == NULL )
{
DPF(0,("tmman:halCreate:objectAllocate:FAIL\n" ));
Status = statusObjectAllocFail;
goto halCreateExit1;
}
Hal->SelfInterrupt = ((halParameters*)Parameters)->PCIIrq;// from Target -> Host
Hal->PeerInterrupt = ((halParameters*)Parameters)->TMIrq;// Host -> Target
Hal->Handler = Null;
Hal->Context = Null;
Hal->Swapping = False; // target running in same endianness
Hal->TMDeviceVendorID = ((halParameters*)Parameters)->TMDeviceVendorID;
Hal->TMSubsystemID = ((halParameters*)Parameters)->TMSubsystemID;
Hal->TMClassRevisionID = ((halParameters*)Parameters)->TMClassRevisionID;
Hal->BridgeDeviceVendorID = ((halParameters*)Parameters)->BridgeDeviceVendorID;
Hal->BridgeSubsystemID = ((halParameters*)Parameters)->BridgeSubsystemID;
Hal->BridgeClassRevisionID = ((halParameters*)Parameters)->BridgeClassRevisionID;
//Hal->CPURevision = ((halParameters*)Parameters)->CPURevision;
//Hal->BoardRevision = ((halParameters*)Parameters)->BoardRevision;
/* BEGIN Platform Specific */
Hal->BusNumber = ((halParameters*)Parameters)->BusNumber;
Hal->DeviceNumber = ((halParameters*)Parameters)->DeviceNumber;
Hal->FunctionNumber = ((halParameters*)Parameters)->FunctionNumber;
Hal->DSPNumber = ((halParameters*)Parameters)->DSPNumber;
Hal->MMIOAddrPhysical = ((halParameters*)Parameters)->MMIOAddrPhysical;
Hal->MMIOLength = ((halParameters*)Parameters)->MMIOLength;
Hal->SDRAMAddrPhysical = ((halParameters*)Parameters)->SDRAMAddrPhysical;
Hal->SDRAMLength = ((halParameters*)Parameters)->SDRAMLength;
Hal->Control = ((halParameters*)Parameters)->SharedData;
Hal->SpeculativeLoadFix = ((halParameters*)Parameters)->SpeculativeLoadFix;
Hal->MMIOHostAddrPhysical = Hal->MMIOAddrPhysical;
Hal->SDRAMHostAddrPhysical = Hal->SDRAMAddrPhysical;
// get a handle to the physical memory for mapping user sections
Hal->MMIOAddrKernel = (PUCHAR)winMapPhysToLinear (
Hal->MMIOHostAddrPhysical.LowPart,
Hal->MMIOLength,
0 );
if (Hal->MMIOAddrKernel == (PUCHAR)0xFFFFFFFF)
{
DPF(0,("tmman:halCreate:winMapPhysToLinear:MMIO:FAIL\n" ));
goto halCreateExit2;
}
if ( TMManGlobal->MapSDRAM )
{
Hal->SDRAMAddrKernel = (PUCHAR)winMapPhysToLinear (
Hal->SDRAMHostAddrPhysical.LowPart,
Hal->SDRAMLength,
0 );
if (Hal->SDRAMAddrKernel == (PUCHAR)0xFFFFFFFF)
{
DPF(0,("tmman:halCreate:winMapPhysToLinear:SDRAM:FAIL\n" ));
goto halCreateExit2;
}
}
if ( ((halParameters*)Parameters)->BridgeDeviceVendorID ==
( ( constTMMANDECBridgeDeviceID << 16 ) | constTMMANDECBridgeVendorID ) )
{
Hal->Offset = ((halParameters*)Parameters)->SystemBaseAddress;
/*
Modify the physical addresses for SDRAM and MMIO to reflect actual
address on the trimedia. After this point only relocation software
is going to use physical addresses. Host based software is going to
use linear addresses
*/
Hal->MMIOAddrPhysical.LowPart = ((halParameters*)Parameters)->MMIOBaseAddress;
Hal->SDRAMAddrPhysical.LowPart = ((halParameters*)Parameters)->SDRAMBaseAddress;
}
else
{
Hal->Offset = 0;
}
// NM added code ends
/* do the interrupt stuff */
IRQDescriptors.VID_IRQ_Number = ((halParameters*)Parameters)->InterruptVector;
IRQDescriptors.VID_Options = VPICD_OPT_CAN_SHARE | VPICD_OPT_SHARE_PMODE_ONLY | VPICD_OPT_REF_DATA;
IRQDescriptors.VID_Hw_Int_Proc = (DWORD)vxdIRQHandlerA;
IRQDescriptors.VID_Virt_Int_Proc = 0;
IRQDescriptors.VID_EOI_Proc = 0;
IRQDescriptors.VID_Mask_Change_Proc = 0;
IRQDescriptors.VID_IRET_Proc = 0;
IRQDescriptors.VID_IRET_Time_Out = 500;
IRQDescriptors.VID_Hw_Int_Ref = (DWORD)Hal;
Hal->InterruptObject =
winVPICD_Virtualize_IRQ( &IRQDescriptors );
if ( ! Hal->InterruptObject )
{
DPF(0,("tmman:halCreate:winVPICD_Virtualize_IRQ:FAIL\n"));
goto halCreateExit2;
}
winVPICD_Physically_Unmask( Hal->InterruptObject );
for ( Idx = 0 ; Idx < constTMMANPCIRegisters ; Idx ++ )
{
Hal->PCIRegisters[Idx] =
((halParameters*)Parameters)->PCIRegisters[Idx];
}
/* do this only if we have to run in INTEL MODE */
// assume TM1S+
if ( ( *(PULONG)(Hal->MMIOAddrKernel + BIU_CTL) &
(constTMManBIU_CTL_SE | constTMManBIU_CTL_BO | constTMManBIU_CTL_HE) ) == 0x0 )
{ // virgin biu control
ULONG SwappedBIUControl;
UCHAR TempByte;
SwappedBIUControl =
( constTMManBIU_CTL_SE | constTMManBIU_CTL_BO | constTMManBIU_CTL_HE | constTMManBIU_CTL_SR );
// do a dword swap
TempByte = ((PUCHAR)&SwappedBIUControl)[0];
((PUCHAR)&SwappedBIUControl)[0] = ((PUCHAR)&SwappedBIUControl)[3];
((PUCHAR)&SwappedBIUControl)[3] = TempByte;
TempByte = ((PUCHAR)&SwappedBIUControl)[1];
((PUCHAR)&SwappedBIUControl)[1] = ((PUCHAR)&SwappedBIUControl)[2];
((PUCHAR)&SwappedBIUControl)[2] = TempByte;
*(PULONG)(Hal->MMIOAddrKernel + BIU_CTL) = SwappedBIUControl;
Hal->FirstTimeReset = TRUE;
}
else
{
Hal->FirstTimeReset = FALSE;
}
// set the cache details every time this function is called
*(PULONG)(Hal->MMIOAddrKernel + DRAM_LIMIT) = Hal->SDRAMAddrPhysical.LowPart + Hal->SDRAMLength;
//this->MMIO.pCache->dwDRAMCacheableLimit = this->dwSDRAMPhys;
*(PULONG)(Hal->MMIOAddrKernel + DRAM_CACHEABLE_LIMIT) = Hal->SDRAMAddrPhysical.LowPart + Hal->SDRAMLength;
*(PULONG)(Hal->MMIOAddrKernel + ICLEAR) = (ULONG)(0x0);
*(PULONG)(Hal->MMIOAddrKernel + IMASK) = (ULONG)(~0x0);
*HalHandlePointer = (UInt32)Hal;
halDumpObject ( (UInt32)Hal );
return statusSuccess;
/* SEH code */
/*
halCreateExit3:
winVPICD_Physically_Mask ( Hal->InterruptObject );
winVPICD_Force_Default_Behavior ( Hal->InterruptObject );
*/
halCreateExit2:
objectFree ( Hal );
halCreateExit1:
return Status;
}
TMStatus halDestroy (
UInt32 HalHandle )
{
HalObject* Hal = (HalObject*)HalHandle;
if ( objectValidate ( Hal, HalFourCC ) != True )
{
DPF(0,("tmman:halDestroy:objectValidate:FAIL\n" ));
return statusInvalidHandle;
}
winVPICD_Physically_Mask ( Hal->InterruptObject );
winVPICD_Force_Default_Behavior ( Hal->InterruptObject );
objectFree ( Hal );
return statusSuccess;;
}
TMStatus halReset (
UInt32 HalHandle )
{
HalObject* Hal = (HalObject*)HalHandle;
if ( objectValidate ( Hal, HalFourCC ) != True )
{
DPF(0,("tmman:halReset:objectValidate:FAIL\n" ));
return statusInvalidHandle;
}
Hal->Control->HostInterruptSpinLock =
halAccess32 ( HalHandle, False );
Hal->Control->TargetInterruptSpinLock =
halAccess32 ( HalHandle, False );
return statusSuccess;
}
TMStatus halSetPeerVersion (
UInt32 HalHandle,
UInt32 MajorVersion,
UInt32 MinorVersion )
{
HalObject* Hal = (HalObject*)HalHandle;
if ( objectValidate ( Hal, HalFourCC ) != True )
{
DPF(0,("tmman:halSetPeerVersion:objectValidate:FAIL\n" ));
return statusInvalidHandle;
}
Hal->PeerMajorVersion = MajorVersion;
Hal->PeerMinorVersion = MinorVersion;
return statusSuccess;
}
TMStatus halGetPeerVersion (
UInt32 HalHandle,
UInt32* MajorVersionPtr,
UInt32* MinorVersionPtr )
{
HalObject* Hal = (HalObject*)HalHandle;
if ( objectValidate ( Hal, HalFourCC ) != True )
{
DPF(0,("tmman:halGetPeerVersion:objectValidate:FAIL\n" ));
return statusInvalidHandle;
}
*MajorVersionPtr = Hal->PeerMajorVersion;
*MinorVersionPtr = Hal->PeerMinorVersion;
return statusSuccess;
}
TMStatus halStartDSP (
UInt32 HalHandle )
{
HalObject* Hal = (HalObject*)HalHandle;
if ( objectValidate ( Hal, HalFourCC ) != True )
{
DPF(0,("tmman:halStartDSP:objectValidate:FAIL\n" ));
return statusInvalidHandle;
}
if ( Hal->SpeculativeLoadFix )
{
/* disable the PCI apperture */
*(PULONG)(Hal->MMIOAddrKernel + DC_LOCK_CTL) =
/* read the value of DC_LOCK_CTL - retain all bits except bits 5 & 6 */
( ( (*(PULONG)(Hal->MMIOAddrKernel + DC_LOCK_CTL)) & (~constTMManDC_LOCK_CTL_MASK) ) |
/* or it with the new values of bits 5 & 6 */
( constTMManDC_LOCK_CTL_MASK & ( ( constTMManDC_LOCK_CTL_PDS ) << constTMManDC_LOCK_CTL_POSITION ) ) );
}
else
{
/* enable the PCI apperture */
*(PULONG)(Hal->MMIOAddrKernel + DC_LOCK_CTL) =
/* read the value of DC_LOCK_CTL - retain all bits except bits 5 & 6 */
( ( (*(PULONG)(Hal->MMIOAddrKernel + DC_LOCK_CTL)) & (~constTMManDC_LOCK_CTL_MASK) ) |
/* or it with the new values of bits 5 & 6 */
( constTMManDC_LOCK_CTL_MASK & ( ( constTMManDC_LOCK_CTL_HEN ) << constTMManDC_LOCK_CTL_POSITION ) ) );
}
// clear the IMask & IClear register
*(PULONG)(Hal->MMIOAddrKernel + ICLEAR) = (ULONG)(0x0);
*(PULONG)(Hal->MMIOAddrKernel + IMASK) = (ULONG)(~0x0);
*(PULONG)(Hal->MMIOAddrKernel + BIU_CTL) &= (~constTMManBIU_CTL_SR);
*(PULONG)(Hal->MMIOAddrKernel + BIU_CTL) |= constTMManBIU_CTL_CR;
return statusSuccess;
}
TMStatus halStopDSP (
UInt32 HalHandle )
{
HalObject* Hal = (HalObject*)HalHandle;
ULONG Idx;
if ( objectValidate ( Hal, HalFourCC ) != True )
{
DPF(0,("tmman:halStopDSP:objectValidate:FAIL\n" ));
return statusInvalidHandle;
}
// biu reset BIU_CTL
*(PULONG)(Hal->MMIOAddrKernel + BIU_CTL) &= (~constTMManBIU_CTL_CR);
*(PULONG)(Hal->MMIOAddrKernel + BIU_CTL) |= constTMManBIU_CTL_SR;
// reset the peripherals
// audio out AO_CTL
*(PULONG)( Hal->MMIOAddrKernel + AO_CTL ) = 0x80000000;
*(PULONG)( Hal->MMIOAddrKernel + AO2_CTL ) = 0x80000000;
// audio in AI_CTL
*(PULONG)( Hal->MMIOAddrKernel +AI_CTL ) = 0x80000000;
*(PULONG)( Hal->MMIOAddrKernel +AI2_CTL ) = 0x80000000;
// video in VI_CTL
*(PULONG)( Hal->MMIOAddrKernel +VI_CTL ) = 0x00080000;
*(PULONG)( Hal->MMIOAddrKernel +VI2_CTL ) = 0x00080000;
// video out VO_CTL
*(PULONG)( Hal->MMIOAddrKernel +VO_CTL ) = 0x80000000;
//ssi SSI_CTL
*(PULONG)( Hal->MMIOAddrKernel +SSI_CTL ) = 0xc0000000;
//SPDIF SDO_CTL
*(PULONG)( Hal->MMIOAddrKernel +SPDO_CTL ) = 0x80000000;
//IIC Slave IICS_CTL
*(PULONG)( Hal->MMIOAddrKernel +IICS_CTL ) = 0x00200000;
// disable
*(PULONG)( Hal->MMIOAddrKernel + IIC_CTL ) &= ~(0x00000001);
//enable
*(PULONG)( Hal->MMIOAddrKernel + IIC_CTL ) |= 0x00000001;
// reset the VLD once
*(PULONG)( Hal->MMIOAddrKernel + VLD_COMMAND ) = 0x00000401;
// reset the HDVO
*(PULONG)( Hal->MMIOAddrKernel + (HDVO_BASE + (0x20 << 1 )) ) = (ULONG)( 3 << 1 );
// reset the transport demux
*(PULONG)( Hal->MMIOAddrKernel + TP1_CTL ) = 0x80000000;
*(PULONG)( Hal->MMIOAddrKernel + TP2_CTL ) = 0x80000000;
//icp ICP_SR
for ( Idx= 0 ; Idx < 10 ; Idx ++ )
{
// do it 10 times just to make sure ....
if ( *( Hal->MMIOAddrKernel + ICP_SR ) & 0x01 )
break;
// changed on usman's request TRC970225
*( Hal->MMIOAddrKernel + ICP_SR ) = 0x80;
}
//jtag JTAG_CTL
*(PULONG)( Hal->MMIOAddrKernel + JTAG_DATA_IN ) = 0x00000000;
*(PULONG)( Hal->MMIOAddrKernel + JTAG_DATA_OUT ) = 0x00000000;
*(PULONG)( Hal->MMIOAddrKernel + JTAG_CTL ) = 0x00000004;
return statusSuccess;
}
TMStatus halResetDSP (
UInt32 HalHandle )
{
HalObject* Hal = (HalObject*)HalHandle;
ULONG Idx;
// we don't write anything into the first 3 registers
// we write the command status at the very end.
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