initc5402.asm

5402DSP程序设计语言

    ;.mmregs
	.include MMRegs.h
	.global _InitC5402,_InitMcBSP0 
	.ref  us_delay ,_ms_delay 
	.global _send_0,_send_1,_send_2,_send_end
_InitC5402:

******* Disable All Interrupts *******
 ;   SSBX  INTM                  ; disable (mask) global(CPU) intrpts 
;   STM   #0x0000, IMR          ; disable peripheral interrupts
  ;  STM   #0xFFFF, IFR          ; clear the intrupts' flags
      	
******* Configure C5402 System Registers *******
      STM   #0x3FE1,PMST
      STM   #0x7FFF, SWWSR        ; 7 wait cycle for IO space &
                                  ;  data&prog spaces 
      STM   #0x0001,SWCR          ; SWSM = 1 Wait states in SWWSR are multiplied by 2                            
      STM   #0x7000,BSCR          ; 0=RES BH=0 The bus holder is disabled.
                                  ; HBH = 0 hpi bus holder is disabled.
                                  ;IACKOFF = 0 The IACK signal output off function is disabled
                                  ;DIVFCT = 11 CLKOUT is divided by 4 from the DSP clock
                                  ;CONSEC = 0 Bank-switching on 32K bank boundaries only.
    STM   #0x1800,ST0           ; ST0 at default setting
    STM   #0x6900,ST1           ; ST1 at default (note:INTX=1)
                ; MC mode&OVLY=1, vectors at 3F80h
                                  ;DROM=1   OVLY=1  
****** Set up Timer Control Registers *******     
      STM   #0x0010, TCR          ; stop on-chip timer0 
      
******* Setup System (CPU) Clock *******      
   ; STM #0, CLKMD ; software setting of DSP clock  PLL OFF  RATIO = 0.5
	; 15  14   13   12  **|     11      |  10  9  8 ** 7  6  5  4 ** 3  |       2        |       1       |       0       |
	;    PLLMUL (R/W)     PLLDIV(R/W)        PLLCOUNT (R/W)               PLLON/OFF(R/W)   PLLNDIV(R/W)     PLLSTATUS(R)
	;STM #0, CLKMD ; (to divider mode before setting)	
	;STM #0x3007, CLKMD ; set C5402 DSP clock to 40MHz  
	nop
	nop
	nop
	stm     #0H, CLKMD 
	nop
	nop
	nop ;switch to DIV mode clkout= 1/2 clkin
    stm      #0F007h, CLKMD ;switch to PLL X 5 mode
statu:
	ldm      CLKMD, A
	and      #01b, A ;poll STATUS bit
	bc       statu, AEQ
	
	nop
	nop
	STM #0,AR5 
   STM   #0FFFFH,IFR
   STM   #0x0101, IMR          ; able MCBSP0 RX TX INTERRUPT
   RSBX  INTM                  ; able (mask) global(CPU) intrpts 
   NOP
  NOP
   RET
		
************************************************************
**** McBSP0 CONFIG GPIO MODE
************************************************************
_InitMcBSP0: 
******* Reset McBSP0                ; able (mask) global(CPU) intrpts 
                                                            
      STM   SPCR1, McBSP0_SPSA
      STM   #0000h, McBSP0_SPSD
      STM   SPCR2, McBSP0_SPSA    ; 
      STM   #0000h, McBSP0_SPSD   ;(XRST=RRST=0)
      NOP                         ; 
      RPT   #1FFFH
      NOP
      STM   PCR, McBSP0_SPSA
      STM   #3000h, McBSP0_SPSD    ;XIOEN = 1 DX, FSX and CLKX are configured as general-purpose I/Os and
                                  ;do not function as serial port pins
                                  ;RIOEN = 1 DR, FSR, CLKR and CLKS are configured as general-purpose I/Os
                                  ;pins and do not function as serial port
      RET
   
**************************************************************
_send_0:	;CS<=DX,C_KEY_7279<=FSR,CLK<=CLKX,DATA<=CLKR(CLKR<=DATA)
     STM   PCR, McBSP0_SPSA	  
     STM   #3F24h, McBSP0_SPSD    ; 1x x100     
     NOP
     NOP
     STM   #3F04h, McBSP0_SPSD   ;  0x x100
     NOP                          ; delay  45us
     RET							;  0xBF
_send_1:
     STM   #3F07h, McBSP0_SPSD    ;0x x111  
     stm #5,ar3
	 call us_delay
     STM   #3F05h, McBSP0_SPSD    ;0x x101     1 
     stm #5,ar3
	 call us_delay
     RET
_send_2:
     STM   #3F06h, McBSP0_SPSD    ;0x x110 
     stm #5,ar3
	 call us_delay
     STM   #3F04h, McBSP0_SPSD    ;0x x100     2
     stm #5,ar3
	 call us_delay
	 RET
_send_end:
     STM   #3F24h, McBSP0_SPSD    ;1x x100   
     stm #5,ar3
	 call us_delay 
     RET
   
**************************************************************