int3_isr.asm

5402DSP程序设计语言

    ;.mmregs
	.include MMRegs.h
	.global _INT3_ISR ,write_7279 
	.ref  us_delay ,_ms_delay 
	;.bss 	_key_code_vlue,1,0,0
************************************************************** 
_INT3_ISR:
       ;CS<=DX, C_KEY_7279<=FSR, CLK<=CLKX, DATA<=CLKR(CLKR<=DATA)
     LD     #0, DP               ; reset data-page pointer
            
     STM   #0x2900,ST1           ; ST1 at default (note:INTX=1
******* Disable All Interrupts *******
     SSBX  INTM                  ; disable (mask) global(CPU) intrpts 
     STM   #0x0000, IMR          ; disable peripheral interrupts
     STM   #0xFFFF, IFR          ; clear the intrupts' flags
      
     STM #0,AR6 
     
     STM   PCR, McBSP0_SPSA	  
     STM   #3F24h, McBSP0_SPSD    ; 1x x100     
     NOP
     NOP
     STM   #3F04h, McBSP0_SPSD   ;  0x x100
     NOP                          ; delay  45us
     stm #45,ar3
	 call us_delay
	 								;  0x15 + data
     STM   #3F06h, McBSP0_SPSD    ;0x x110  
     stm #18,ar3
	 call us_delay
     STM   #3F04h, McBSP0_SPSD    ;0x x100     1 
     
     stm #20,ar3
	 call us_delay
     STM   #3F06h, McBSP0_SPSD    ;0x x110 
     stm #18,ar3
	 call us_delay
     STM   #3F04h, McBSP0_SPSD    ;0x x100     2 
     
     stm #20,ar3
	 call us_delay
     STM   #3F06h, McBSP0_SPSD    ;0x x110  
     stm #18,ar3
	 call us_delay
     STM   #3F04h, McBSP0_SPSD    ;0x x100     3 
     
     stm #20,ar3
	 call us_delay
     STM   #3F07h, McBSP0_SPSD    ;0x x111  
     stm #18,ar3
	 call us_delay
     STM   #3F05h, McBSP0_SPSD    ;0x x101     4 
     
     stm #20,ar3
	 call us_delay
     STM   #3F06h, McBSP0_SPSD    ;0x x110  
     stm #18,ar3
	 call us_delay
     STM   #3F04h, McBSP0_SPSD    ;0x x100     5 
     
     stm #20,ar3
	 call us_delay
     STM   #3F07h, McBSP0_SPSD    ;0x x111  
     stm #18,ar3
	 call us_delay
     STM   #3F05h, McBSP0_SPSD    ;0x x101     6 
     
     stm #20,ar3
	 call us_delay 
     STM   #3F06h, McBSP0_SPSD    ;0x x110  
     stm #18,ar3
	 call us_delay
     STM   #3F04h, McBSP0_SPSD    ;0x x100     7
      
     stm #20,ar3
	 call us_delay
     STM   #3F07h, McBSP0_SPSD    ;0x x111  
     stm #18,ar3
	 call us_delay
     STM   #3F05h, McBSP0_SPSD    ;0x x101     8 
     stm #20,ar3
	 call us_delay
     STM   #3F04h, McBSP0_SPSD    ;0x x100 
     stm #8,ar3
	 call us_delay
     STM   #3F05h, McBSP0_SPSD    ;0x x101       
          ;CS<=DX,      C_KEY_7279<=FSR,   CLK<=CLKX,  DATA<=CLKR(CLKR<=DATA)
    
     nop
     nop
     stm #80,ar3
	 call us_delay
     nop
     STM   #3F03h, McBSP0_SPSD    ;0x x011 
     stm #5,ar3
	 call us_delay 
     STM   #3E02h, McBSP0_SPSD    ;0x x01x 
     stm #20,ar3
	 call us_delay 
     LDM McBSP0_SPSD,A
     AND  #0001h,A 
     SFTL A,+7  
     STL A,AR6                         
     STM   #3E00h, McBSP0_SPSD    ;0x x00x 		9
     
     stm #18,ar3
	 call us_delay
     STM   #3E02h, McBSP0_SPSD    ;0x x01x
     stm #20,ar3
	 call us_delay  
     PSHM B 
     LD #0,B
     LDM McBSP0_SPSD,A
     AND  #0001h,A   
     SFTL A,+6,B
     LDM AR6,A
     OR B,A 
     STL A,AR6 
     POPM B
     STM   #3E00h, McBSP0_SPSD    ;0x x00x 		10
     
     stm #18,ar3
	 call us_delay
     STM   #3E02h, McBSP0_SPSD    ;0x x01x 
     stm #20,ar3
	 call us_delay 
     PSHM B 
     LD #0,B
     LDM McBSP0_SPSD,A
     AND  #0001h,A   
     SFTL A,+5,B
     LDM AR6,A
     OR B,A 
     STL A,AR6 
     POPM B
     STM   #3E00h, McBSP0_SPSD    ;0x x00x 		11
     
     stm #18,ar3
	 call us_delay
     STM   #3E02h, McBSP0_SPSD    ;0x x01x 
     stm #20,ar3
	 call us_delay 
     PSHM B 
     LD #0,B
     LDM McBSP0_SPSD,A
     AND  #0001h,A   
     SFTL A,+4,B
     LDM AR6,A
     OR B,A 
     STL A,AR6 
     POPM B
     STM   #3E00h, McBSP0_SPSD    ;0x x00x 		12
     
     stm #18,ar3
	 call us_delay
     STM   #3E02h, McBSP0_SPSD    ;0x x01x 
     stm #20,ar3
	 call us_delay 
     PSHM B 
     LD #0,B
     LDM McBSP0_SPSD,A
     AND  #0001h,A   
     SFTL A,+3,B
     LDM AR6,A
     OR B,A 
     STL A,AR6 
     POPM B
     STM   #3E00h, McBSP0_SPSD    ;0x x00x 		13
     
     stm #18,ar3
	 call us_delay
     STM   #3E02h, McBSP0_SPSD    ;0x x01x 
     stm #20,ar3
	 call us_delay 
     PSHM B 
     LD #0,B
     LDM McBSP0_SPSD,A
     AND  #0001h,A   
     SFTL A,+2,B
     LDM AR6,A
     OR B,A 
     STL A,AR6 
     POPM B 
     STM   #3E00h, McBSP0_SPSD    ;0x x00x 		14
     
     stm #18,ar3
	 call us_delay
     STM   #3E02h, McBSP0_SPSD    ;0x x01x 
     stm #20,ar3
	 call us_delay 
     PSHM B 
     LD #0,B
     LDM McBSP0_SPSD,A
     AND  #0001h,A   
     SFTL A,+1,B
     LDM AR6,A
     OR B,A 
     STL A,AR6 
     POPM B
     STM   #3E00h, McBSP0_SPSD    ;0x x00x 		15
     
     stm #18,ar3
	 call us_delay
     STM   #3E02h, McBSP0_SPSD    ;0x x01x 
     stm #20,ar3
	 call us_delay 
     PSHM B 
     LD #0,B
     LDM McBSP0_SPSD,A
     AND  #0001h,A   
     SFTL A,+0,B
     LDM AR6,A
     OR B,A 
     STL A,AR5 
     POPM B
     STM   #3F04h, McBSP0_SPSD    ;0x x100 		16
                          
     stm #40,ar3
	 call us_delay 
	 STM   #3F24h, McBSP0_SPSD    ;1x x110 		
     NOP
    nop
 ;   call write_7279
	nop      
    STM   #0x6900,ST1           ; ST1 at default (note:INTX=1
    STM   #0FFFFH,IFR
    STM   #0x0101, IMR          ; able MCBSP0 RX TX INTERRUPT
    RSBX  INTM                  ; able (mask) global(CPU) intrpts 
	NOP
	NOP
    NOP
    RET