xl36pwm1.asm

68HC08XL36 Timer Interface Module in an unbuffered PWM example

*
* This software will feature the 68HC08XL36 Timer Interface Module in an
* unbuffered PWM example.  A periodic waveform with specified duty cycle 
* and period will be generated on a specified channel.
* Assembled with IASM08 Ver. 3.03
*
* Register Equates
TSC		equ $20	; Timer Status & Control Register $20
TDMA		equ $21	; Timer DMA Select Register $21
TCNTH		equ $22	; Timer Counter Register Hi $22
TCNTL		equ $23	; Timer Counter Register Lo $23
TMODH		equ $24	; Timer Counter Modulo Register Hi $24
TMODL		equ $25	; Timer Counter Modulo Register Lo $25
TSC0		equ $26	; Timer Channel 0 Status & Control Register $26
TCH0H		equ $27	; Timer Channel 0 Register Hi $27
TCH0L		equ $28	; Timer Channel 0 Register Lo $28
TSC1		equ $29	; Timer Channel 1 Status & Control Register $29
TCH1H		equ $2A	; Timer Channel 1 Register Hi $2a
TCH1L		equ $2B	; Timer Channel 1 Register Lo $2b
TSC2		equ $2C	; Timer Channel 2 Status & Control Register $2c
TCH2H		equ $2D	; Timer Channel 2 Register Hi $2d
TCH2L		equ $2E	; Timer Channel 2 Register Lo $2e
TSC3		equ $2F	; Timer Channel 3 Status & Control Register $2f
TCH3H		equ $30	; Timer Channel 3 Register Hi $30
TCH3L		equ $31	; Timer Channel 3 Register Lo $31

PORTE		equ $08	; Port E, TIM port

* Misc Equates
BIT0		equ $00
BIT1		equ $01
BIT2		equ $02
BIT3		equ $03
BIT4		equ $04
BIT5		equ $05
BIT6		equ $06
BIT7		equ $07
CHOFFSET	equ $00	; ch0=0 offset, ch1=3 offset, chx=3x offset
DUTYHI	equ $80	; 50% duty cycle
DUTYLO	equ $00
PERHI		equ $FF	; 8.2ms period
PERLO		equ $FF

* TIM status and control register bits
PRESCLR 	equ $00	; prescaler xxxxx000 (bus clock/1)
TOE		equ $00	; timer overflow interrupt enable x0xxxxxx

* Channel x status and control register bits
CHIE		equ $40	; channel interrupt enable x0xxxxxx
MOD		equ $10	; mode select bits xx00xxxx (unbuffered)
EDG		equ $0C	; edge select bits xxxx00xx (set output)
TOV		equ $02	; toggle on overflow bit xxxxxx0x

* Variables in RAM
		org $0050	; start of RAM

* Application assembly code
		org $6E00	; start of ROM
UNBUF_INIT:
* set up channel x for unbuffered PWM
	mov #TOE+$30+PRESCLR,TSC	; stop and reset TIM, select
						; prescaler, TOE
	ldx  #TSC0+CHOFFSET		; point to channel x SCR (H reg=00)'	lda  #CHIE+MOD+EDG+TOV		; enable I, OC, set output, toggle
	sta  ,x				; store channel ICAP control info
	lda  #DUTYHI			; specified duty cycle
	sta  1,x				; store in timer channel reg.
	lda #DUTYLO
	sta  2,x

	mov #PERHI,TMODH			; store specified period
	mov #PERLO,TMODL

	cli					; enable CPU interrupts (delete this
						; line if polling)
	bclr BIT5,TSC			; enable timer counter
	bra  *				; wait for interrupt (to poll
						; monitor channel x flag)
*  channel x interrupt service routine for Ocx

CHISR		equ *
		pshh				; save h register
		lda  TSC0+CHOFFSET	; read channel x flag
		bclr BIT7,TSC0+CHOFFSET	; clear it
*  change duty cycle here (write to channel register)
		pulh				; retrieve h register
		rti				; return from interrupt routine

*  Application vectors
		org  $ffee
		fdb  CHISR
		fdb  CHISR
		fdb  CHISR
		fdb  CHISR

		org  $fffe
		fdb  UNBUF_INIT