cdkzq.rpt

彩灯显示控制,五个花样,可独立也可循环显示

         #  _LC8_C12;

-- Node name is '|XSKZ:U2|:57' = '|XSKZ:U2|FLOWER1' 
-- Equation name is '_LC2_C14', type is buried 
_LC2_C14 = DFFE( _EQ036,  _LC7_A4,  VCC,  VCC, !_LC3_C24);
  _EQ036 =  _LC4_C21 & !_LC7_C14
         #  _LC4_C14 & !_LC7_C14;

-- Node name is '|XSKZ:U2|:56' = '|XSKZ:U2|FLOWER2' 
-- Equation name is '_LC5_C12', type is buried 
_LC5_C12 = DFFE( _EQ037,  _LC7_A4,  VCC,  VCC, !_LC3_C24);
  _EQ037 =  _LC3_C14 &  _LC4_C21;

-- Node name is '|XSKZ:U2|:55' = '|XSKZ:U2|FLOWER3' 
-- Equation name is '_LC7_C12', type is buried 
_LC7_C12 = DFFE( _EQ038,  _LC7_A4,  VCC,  VCC, !_LC3_C24);
  _EQ038 =  _LC2_C12 &  _LC6_C22
         #  _LC2_C12 &  _LC8_C16;

-- Node name is '|XSKZ:U2|:54' = '|XSKZ:U2|FLOWER4' 
-- Equation name is '_LC1_C6', type is buried 
_LC1_C6  = DFFE( _EQ039,  _LC7_A4,  VCC,  VCC, !_LC3_C24);
  _EQ039 =  _LC2_C16 &  _LC2_C22;

-- Node name is '|XSKZ:U2|:53' = '|XSKZ:U2|FLOWER5' 
-- Equation name is '_LC1_C8', type is buried 
_LC1_C8  = DFFE( _EQ040,  _LC7_A4,  VCC,  VCC, !_LC3_C24);
  _EQ040 = !_LC1_C16 &  _LC1_C22 &  _LC2_C16;

-- Node name is '|XSKZ:U2|:52' = '|XSKZ:U2|FLOWER6' 
-- Equation name is '_LC4_C10', type is buried 
_LC4_C10 = DFFE( _EQ041,  _LC7_A4,  VCC,  VCC, !_LC3_C24);
  _EQ041 = !_LC1_C16 & !_LC2_C24 &  _LC4_C22;

-- Node name is '|XSKZ:U2|:51' = '|XSKZ:U2|FLOWER7' 
-- Equation name is '_LC6_C12', type is buried 
_LC6_C12 = DFFE( _EQ042,  _LC7_A4,  VCC,  VCC, !_LC3_C24);
  _EQ042 = !_LC3_C14
         #  _LC8_C12
         #  _LC6_C22;

-- Node name is '|XSKZ:U2|:50' = '|XSKZ:U2|FLOWER8' 
-- Equation name is '_LC5_C14', type is buried 
_LC5_C14 = DFFE( _EQ043,  _LC7_A4,  VCC,  VCC, !_LC3_C24);
  _EQ043 =  _LC4_C21 & !_LC7_C14
         #  _LC4_C14 & !_LC7_C14;

-- Node name is '|XSKZ:U2|:49' = '|XSKZ:U2|FLOWER9' 
-- Equation name is '_LC6_C16', type is buried 
_LC6_C16 = DFFE( _EQ044,  _LC7_A4,  VCC,  VCC, !_LC3_C24);
  _EQ044 =  _LC3_C14 &  _LC8_C12;

-- Node name is '|XSKZ:U2|:48' = '|XSKZ:U2|FLOWER10' 
-- Equation name is '_LC3_C16', type is buried 
_LC3_C16 = DFFE( _EQ045,  _LC7_A4,  VCC,  VCC, !_LC3_C24);
  _EQ045 =  _LC2_C12 &  _LC8_C16;

-- Node name is '|XSKZ:U2|:47' = '|XSKZ:U2|FLOWER11' 
-- Equation name is '_LC2_C17', type is buried 
_LC2_C17 = DFFE( _EQ046,  _LC7_A4,  VCC,  VCC, !_LC3_C24);
  _EQ046 =  _LC2_C16 &  _LC6_C22
         #  _LC2_C16 &  _LC2_C22;

-- Node name is '|XSKZ:U2|:46' = '|XSKZ:U2|FLOWER12' 
-- Equation name is '_LC4_C17', type is buried 
_LC4_C17 = DFFE( _EQ047,  _LC7_A4,  VCC,  VCC, !_LC3_C24);
  _EQ047 = !_LC1_C16 &  _LC1_C22 &  _LC2_C16;

-- Node name is '|XSKZ:U2|:45' = '|XSKZ:U2|FLOWER13' 
-- Equation name is '_LC1_C20', type is buried 
_LC1_C20 = DFFE( _EQ048,  _LC7_A4,  VCC,  VCC, !_LC3_C24);
  _EQ048 = !_LC1_C16 & !_LC2_C24 &  _LC4_C22;

-- Node name is '|XSKZ:U2|:44' = '|XSKZ:U2|FLOWER14' 
-- Equation name is '_LC5_C21', type is buried 
_LC5_C21 = DFFE( _EQ049,  _LC7_A4,  VCC,  VCC, !_LC3_C24);
  _EQ049 = !_LC3_C14
         #  _LC8_C12
         #  _LC6_C22;

-- Node name is '|XSKZ:U2|:43' = '|XSKZ:U2|FLOWER15' 
-- Equation name is '_LC6_C14', type is buried 
_LC6_C14 = DFFE( _EQ050,  _LC7_A4,  VCC,  VCC, !_LC3_C24);
  _EQ050 =  _LC4_C21 & !_LC7_C14
         #  _LC4_C14 & !_LC7_C14;

-- Node name is '|XSKZ:U2|:42' = '|XSKZ:U2|FLOWER16' 
-- Equation name is '_LC5_C24', type is buried 
_LC5_C24 = DFFE( _EQ051,  _LC7_A4,  VCC,  VCC, !_LC3_C24);
  _EQ051 =  _LC3_C14 &  _LC4_C21;

-- Node name is '|XSKZ:U2|:41' = '|XSKZ:U2|FLOWER17' 
-- Equation name is '_LC4_C12', type is buried 
_LC4_C12 = DFFE( _EQ052,  _LC7_A4,  VCC,  VCC, !_LC3_C24);
  _EQ052 =  _LC2_C12 &  _LC8_C16;

-- Node name is '|XSKZ:U2|:40' = '|XSKZ:U2|FLOWER18' 
-- Equation name is '_LC3_C17', type is buried 
_LC3_C17 = DFFE( _EQ053,  _LC7_A4,  VCC,  VCC, !_LC3_C24);
  _EQ053 =  _LC2_C16 &  _LC6_C22
         #  _LC2_C16 &  _LC2_C22;

-- Node name is '|XSKZ:U2|:39' = '|XSKZ:U2|FLOWER19' 
-- Equation name is '_LC1_C24', type is buried 
_LC1_C24 = DFFE( _EQ054,  _LC7_A4,  VCC,  VCC, !_LC3_C24);
  _EQ054 = !_LC1_C16 &  _LC1_C22 &  _LC2_C16;

-- Node name is '|XSKZ:U2|:38' = '|XSKZ:U2|FLOWER20' 
-- Equation name is '_LC6_C24', type is buried 
_LC6_C24 = DFFE( _EQ055,  _LC7_A4,  VCC,  VCC, !_LC3_C24);
  _EQ055 = !_LC1_C16 & !_LC2_C24 &  _LC4_C22;

-- Node name is '|XSKZ:U2|:37' = '|XSKZ:U2|FLOWER21' 
-- Equation name is '_LC3_C12', type is buried 
_LC3_C12 = DFFE( _EQ056,  _LC7_A4,  VCC,  VCC, !_LC3_C24);
  _EQ056 =  _LC8_C16
         #  _LC5_C16
         # !_LC3_C14;

-- Node name is '|XSKZ:U2|:36' = '|XSKZ:U2|FLOWER22' 
-- Equation name is '_LC1_C14', type is buried 
_LC1_C14 = DFFE( _EQ057,  _LC7_A4,  VCC,  VCC, !_LC3_C24);
  _EQ057 =  _LC4_C21 & !_LC7_C14
         #  _LC4_C14 & !_LC7_C14;

-- Node name is '|XSKZ:U2|:35' = '|XSKZ:U2|FLOWER23' 
-- Equation name is '_LC8_C14', type is buried 
_LC8_C14 = DFFE( _EQ058,  _LC7_A4,  VCC,  VCC, !_LC3_C24);
  _EQ058 = !_LC4_C14 &  _LC4_C21 & !_LC7_C14;

-- Node name is '|XSKZ:U2|:34' = '|XSKZ:U2|FLOWER24' 
-- Equation name is '_LC4_C16', type is buried 
_LC4_C16 = DFFE( _EQ059,  _LC7_A4,  VCC,  VCC, !_LC3_C24);
  _EQ059 =  _LC2_C12 &  _LC2_C22
         #  _LC2_C12 &  _LC7_C16;

-- Node name is '|XSKZ:U2|:33' = '|XSKZ:U2|FLOWER25' 
-- Equation name is '_LC2_C6', type is buried 
_LC2_C6  = DFFE( _EQ060,  _LC7_A4,  VCC,  VCC, !_LC3_C24);
  _EQ060 =  _LC2_C16 &  _LC6_C22
         #  _LC2_C16 &  _LC2_C22;

-- Node name is '|XSKZ:U2|:32' = '|XSKZ:U2|FLOWER26' 
-- Equation name is '_LC1_C17', type is buried 
_LC1_C17 = DFFE( _EQ061,  _LC7_A4,  VCC,  VCC, !_LC3_C24);
  _EQ061 = !_LC1_C16 &  _LC1_C22 &  _LC2_C16;

-- Node name is '|XSKZ:U2|:31' = '|XSKZ:U2|FLOWER27' 
-- Equation name is '_LC4_C24', type is buried 
_LC4_C24 = DFFE( _EQ062,  _LC7_A4,  VCC,  VCC, !_LC3_C24);
  _EQ062 = !_LC1_C16 & !_LC2_C24 &  _LC4_C22;

-- Node name is '|XSKZ:U2|~1034~1' 
-- Equation name is '_LC6_C22', type is buried 
-- synthesized logic cell 
_LC6_C22 = LCELL( _EQ063);
  _EQ063 = !_LC8_C22
         #  _LC7_C22;

-- Node name is '|XSKZ:U2|~1078~1' 
-- Equation name is '_LC4_C22', type is buried 
-- synthesized logic cell 
_LC4_C22 = LCELL( _EQ064);
  _EQ064 =  _LC2_C16 &  _LC6_C22
         #  _LC2_C16 &  _LC5_C22;

-- Node name is '|XSKZ:U2|:1110' 
-- Equation name is '_LC1_C22', type is buried 
_LC1_C22 = LCELL( _EQ065);
  _EQ065 =  _LC6_C22
         #  _LC5_C22
         #  _LC2_C24;

-- Node name is '|XSKZ:U2|~1142~1' 
-- Equation name is '_LC3_C14', type is buried 
-- synthesized logic cell 
!_LC3_C14 = _LC3_C14~NOT;
_LC3_C14~NOT = LCELL( _EQ066);
  _EQ066 =  _LC7_C14
         #  _LC4_C14;

-- Node name is '|XSKZ:U2|~1205~1' 
-- Equation name is '_LC2_C16', type is buried 
-- synthesized logic cell 
_LC2_C16 = LCELL( _EQ067);
  _EQ067 =  _LC2_C12 & !_LC7_C16;

-- Node name is '|XSKZ:U2|:1248' 
-- Equation name is '_LC8_C16', type is buried 
_LC8_C16 = LCELL( _EQ068);
  _EQ068 =  _LC2_C22
         #  _LC7_C16;

-- Node name is '|XSKZ:U2|~1268~1' 
-- Equation name is '_LC2_C12', type is buried 
-- synthesized logic cell 
_LC2_C12 = LCELL( _EQ069);
  _EQ069 =  _LC3_C14 & !_LC5_C16;

-- Node name is '|XSKZ:U2|:1317' 
-- Equation name is '_LC4_C21', type is buried 
_LC4_C21 = LCELL( _EQ070);
  _EQ070 =  _LC6_C22
         #  _LC8_C12;

-- Node name is '|XSKZ:U2|:2199' 
-- Equation name is '_LC8_C12', type is buried 
_LC8_C12 = LCELL( _EQ071);
  _EQ071 =  _LC8_C16
         #  _LC5_C16;

-- Node name is '|XSKZ:U2|:2502' 
-- Equation name is '_LC2_C22', type is buried 
_LC2_C22 = LCELL( _EQ072);
  _EQ072 =  _LC2_C24
         #  _LC1_C16
         #  _LC5_C22;



Project Information                                       f:\caideng\cdkzq.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:01
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:05


Memory Allocated
-----------------

Peak memory allocated during compilation  = 14,597K