📄 cdkzq.rpt
字号:
2 - - - -- INPUT G 0 0 0 0 CLK_IN
17 - - A -- INPUT 0 0 0 17 CLR
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\caideng\cdkzq.rpt
cdkzq
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
27 - - C -- OUTPUT 0 1 0 0 LED0
28 - - C -- OUTPUT 0 1 0 0 LED1
29 - - C -- OUTPUT 0 1 0 0 LED2
30 - - C -- OUTPUT 0 1 0 0 LED3
35 - - - 06 OUTPUT 0 1 0 0 LED4
36 - - - 07 OUTPUT 0 1 0 0 LED5
37 - - - 09 OUTPUT 0 1 0 0 LED6
39 - - - 11 OUTPUT 0 1 0 0 LED7
47 - - - 14 OUTPUT 0 1 0 0 LED8
48 - - - 15 OUTPUT 0 1 0 0 LED9
49 - - - 16 OUTPUT 0 1 0 0 LED10
50 - - - 17 OUTPUT 0 1 0 0 LED11
51 - - - 18 OUTPUT 0 1 0 0 LED12
52 - - - 19 OUTPUT 0 1 0 0 LED13
54 - - - 21 OUTPUT 0 1 0 0 LED14
58 - - C -- OUTPUT 0 1 0 0 LED15
59 - - C -- OUTPUT 0 1 0 0 LED16
60 - - C -- OUTPUT 0 1 0 0 LED17
61 - - C -- OUTPUT 0 1 0 0 LED18
62 - - C -- OUTPUT 0 1 0 0 LED19
64 - - B -- OUTPUT 0 1 0 0 LED20
66 - - B -- OUTPUT 0 1 0 0 LED21
67 - - B -- OUTPUT 0 1 0 0 LED22
70 - - A -- OUTPUT 0 1 0 0 LED23
71 - - A -- OUTPUT 0 1 0 0 LED24
72 - - A -- OUTPUT 0 1 0 0 LED25
73 - - A -- OUTPUT 0 1 0 0 LED26
78 - - - 24 OUTPUT 0 1 0 0 LED27
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\caideng\cdkzq.rpt
cdkzq
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - C 24 SOFT s ! 1 0 0 28 CLR~1
- 2 - A 06 OR2 ! 0 3 0 6 |SXKZ:U1|LPM_ADD_SUB:77|addcore:adder|:59
- 3 - A 03 OR2 0 2 0 4 |SXKZ:U1|LPM_ADD_SUB:77|addcore:adder|:67
- 4 - A 06 OR2 0 3 0 4 |SXKZ:U1|LPM_ADD_SUB:77|addcore:adder|:68
- 7 - A 04 DFFE + 1 3 0 42 |SXKZ:U1|CLLK (|SXKZ:U1|:6)
- 3 - A 09 DFFE + 1 3 0 7 |SXKZ:U1|TEMP3 (|SXKZ:U1|:9)
- 8 - A 06 DFFE + 1 4 0 5 |SXKZ:U1|TEMP2 (|SXKZ:U1|:10)
- 8 - A 03 DFFE + 1 4 0 6 |SXKZ:U1|TEMP1 (|SXKZ:U1|:11)
- 2 - A 03 DFFE + 1 1 0 5 |SXKZ:U1|TEMP0 (|SXKZ:U1|:12)
- 2 - A 04 AND2 2 0 0 7 |SXKZ:U1|:39
- 6 - A 04 AND2 2 0 0 7 |SXKZ:U1|:44
- 5 - A 04 AND2 2 0 0 6 |SXKZ:U1|:49
- 4 - A 04 OR2 ! 2 0 0 4 |SXKZ:U1|:54
- 3 - A 06 OR2 ! 0 4 0 4 |SXKZ:U1|:62
- 1 - A 06 OR2 ! 0 4 0 4 |SXKZ:U1|:120
- 1 - A 09 OR2 ! 0 2 0 4 |SXKZ:U1|:178
- 2 - A 09 OR2 ! 0 2 0 3 |SXKZ:U1|:236
- 1 - A 04 OR2 2 2 0 1 |SXKZ:U1|:298
- 3 - A 04 OR2 0 4 0 1 |SXKZ:U1|:304
- 8 - A 04 OR2 0 4 0 1 |SXKZ:U1|:310
- 6 - A 09 OR2 0 4 0 1 |SXKZ:U1|:325
- 5 - A 09 AND2 s 0 2 0 1 |SXKZ:U1|~326~1
- 4 - A 09 OR2 0 4 0 1 |SXKZ:U1|:327
- 7 - A 09 OR2 0 4 0 1 |SXKZ:U1|:329
- 1 - A 12 AND2 s 0 2 0 1 |SXKZ:U1|~332~1
- 8 - A 09 OR2 0 4 0 1 |SXKZ:U1|:333
- 5 - A 06 OR2 0 4 0 1 |SXKZ:U1|:337
- 6 - A 06 OR2 0 4 0 1 |SXKZ:U1|:340
- 7 - A 06 OR2 0 4 0 1 |SXKZ:U1|:343
- 4 - A 03 OR2 0 4 0 1 |SXKZ:U1|:352
- 5 - A 03 OR2 0 4 0 1 |SXKZ:U1|:355
- 6 - A 03 AND2 0 3 0 1 |SXKZ:U1|:359
- 7 - A 03 OR2 0 4 0 1 |SXKZ:U1|:363
- 1 - A 03 AND2 s ! 0 4 0 1 |SXKZ:U1|~376~1
- 3 - C 22 DFFE 1 2 0 1 |XSKZ:U2|CURRENT_STATE~1
- 8 - C 22 DFFE 1 2 0 2 |XSKZ:U2|CURRENT_STATE~2
- 7 - C 22 DFFE 1 2 0 2 |XSKZ:U2|CURRENT_STATE~3
- 5 - C 22 DFFE 1 2 0 4 |XSKZ:U2|CURRENT_STATE~4
- 2 - C 24 DFFE 1 2 0 7 |XSKZ:U2|CURRENT_STATE~5
- 1 - C 16 DFFE 1 2 0 10 |XSKZ:U2|CURRENT_STATE~6
- 7 - C 16 DFFE 1 2 0 4 |XSKZ:U2|CURRENT_STATE~7
- 5 - C 16 DFFE 1 2 0 4 |XSKZ:U2|CURRENT_STATE~8
- 4 - C 14 DFFE 1 2 0 7 |XSKZ:U2|CURRENT_STATE~9
- 7 - C 14 DFFE 1 3 0 7 |XSKZ:U2|CURRENT_STATE~10
- 7 - C 24 DFFE 1 1 0 1 |XSKZ:U2|CURRENT_STATE~11
- 4 - C 24 DFFE 0 5 1 0 |XSKZ:U2|FLOWER27 (|XSKZ:U2|:31)
- 1 - C 17 DFFE 0 5 1 0 |XSKZ:U2|FLOWER26 (|XSKZ:U2|:32)
- 2 - C 06 DFFE 0 5 1 0 |XSKZ:U2|FLOWER25 (|XSKZ:U2|:33)
- 4 - C 16 DFFE 0 5 1 0 |XSKZ:U2|FLOWER24 (|XSKZ:U2|:34)
- 8 - C 14 DFFE 0 5 1 0 |XSKZ:U2|FLOWER23 (|XSKZ:U2|:35)
- 1 - C 14 DFFE 0 5 1 0 |XSKZ:U2|FLOWER22 (|XSKZ:U2|:36)
- 3 - C 12 DFFE 0 5 1 0 |XSKZ:U2|FLOWER21 (|XSKZ:U2|:37)
- 6 - C 24 DFFE 0 5 1 0 |XSKZ:U2|FLOWER20 (|XSKZ:U2|:38)
- 1 - C 24 DFFE 0 5 1 0 |XSKZ:U2|FLOWER19 (|XSKZ:U2|:39)
- 3 - C 17 DFFE 0 5 1 0 |XSKZ:U2|FLOWER18 (|XSKZ:U2|:40)
- 4 - C 12 DFFE 0 4 1 0 |XSKZ:U2|FLOWER17 (|XSKZ:U2|:41)
- 5 - C 24 DFFE 0 4 1 0 |XSKZ:U2|FLOWER16 (|XSKZ:U2|:42)
- 6 - C 14 DFFE 0 5 1 0 |XSKZ:U2|FLOWER15 (|XSKZ:U2|:43)
- 5 - C 21 DFFE 0 5 1 0 |XSKZ:U2|FLOWER14 (|XSKZ:U2|:44)
- 1 - C 20 DFFE 0 5 1 0 |XSKZ:U2|FLOWER13 (|XSKZ:U2|:45)
- 4 - C 17 DFFE 0 5 1 0 |XSKZ:U2|FLOWER12 (|XSKZ:U2|:46)
- 2 - C 17 DFFE 0 5 1 0 |XSKZ:U2|FLOWER11 (|XSKZ:U2|:47)
- 3 - C 16 DFFE 0 4 1 0 |XSKZ:U2|FLOWER10 (|XSKZ:U2|:48)
- 6 - C 16 DFFE 0 4 1 0 |XSKZ:U2|FLOWER9 (|XSKZ:U2|:49)
- 5 - C 14 DFFE 0 5 1 0 |XSKZ:U2|FLOWER8 (|XSKZ:U2|:50)
- 6 - C 12 DFFE 0 5 1 0 |XSKZ:U2|FLOWER7 (|XSKZ:U2|:51)
- 4 - C 10 DFFE 0 5 1 0 |XSKZ:U2|FLOWER6 (|XSKZ:U2|:52)
- 1 - C 08 DFFE 0 5 1 0 |XSKZ:U2|FLOWER5 (|XSKZ:U2|:53)
- 1 - C 06 DFFE 0 4 1 0 |XSKZ:U2|FLOWER4 (|XSKZ:U2|:54)
- 7 - C 12 DFFE 0 5 1 0 |XSKZ:U2|FLOWER3 (|XSKZ:U2|:55)
- 5 - C 12 DFFE 0 4 1 0 |XSKZ:U2|FLOWER2 (|XSKZ:U2|:56)
- 2 - C 14 DFFE 0 5 1 0 |XSKZ:U2|FLOWER1 (|XSKZ:U2|:57)
- 1 - C 12 DFFE 0 4 1 0 |XSKZ:U2|FLOWER0 (|XSKZ:U2|:58)
- 6 - C 22 OR2 s 0 2 0 9 |XSKZ:U2|~1034~1
- 4 - C 22 OR2 s 0 3 0 4 |XSKZ:U2|~1078~1
- 1 - C 22 OR2 0 3 0 4 |XSKZ:U2|:1110
- 3 - C 14 OR2 s ! 0 2 0 8 |XSKZ:U2|~1142~1
- 2 - C 16 AND2 s 0 2 0 9 |XSKZ:U2|~1205~1
- 8 - C 16 OR2 0 2 0 5 |XSKZ:U2|:1248
- 2 - C 12 AND2 s 0 2 0 5 |XSKZ:U2|~1268~1
- 4 - C 21 OR2 0 2 0 7 |XSKZ:U2|:1317
- 8 - C 12 OR2 0 2 0 5 |XSKZ:U2|:2199
- 2 - C 22 OR2 0 3 0 6 |XSKZ:U2|:2502
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\caideng\cdkzq.rpt
cdkzq
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 3/ 96( 3%) 14/ 48( 29%) 3/ 48( 6%) 1/16( 6%) 4/16( 25%) 0/16( 0%)
B: 1/ 96( 1%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
C: 18/ 96( 18%) 5/ 48( 10%) 15/ 48( 31%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\caideng\cdkzq.rpt
cdkzq
** CLOCK SIGNALS **
Type Fan-out Name
DFF 43 |SXKZ:U1|CLLK
INPUT 5 CLK_IN
Device-Specific Information: f:\caideng\cdkzq.rpt
cdkzq
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 17 CLR
Device-Specific Information: f:\caideng\cdkzq.rpt
cdkzq
** EQUATIONS **
CHOSE_KEY0 : INPUT;
CHOSE_KEY1 : INPUT;
CLK_IN : INPUT;
CLR : INPUT;
-- Node name is 'CLR~1'
-- Equation name is 'CLR~1', location is LC3_C24, type is buried.
-- synthesized logic cell
!_LC3_C24 = _LC3_C24~NOT;
_LC3_C24~NOT = LCELL(!CLR);
-- Node name is 'LED0'
-- Equation name is 'LED0', type is output
LED0 = _LC1_C12;
-- Node name is 'LED1'
-- Equation name is 'LED1', type is output
LED1 = _LC2_C14;
-- Node name is 'LED2'
-- Equation name is 'LED2', type is output
LED2 = _LC5_C12;
-- Node name is 'LED3'
-- Equation name is 'LED3', type is output
LED3 = _LC7_C12;
-- Node name is 'LED4'
-- Equation name is 'LED4', type is output
LED4 = _LC1_C6;
-- Node name is 'LED5'
-- Equation name is 'LED5', type is output
LED5 = _LC1_C8;
-- Node name is 'LED6'
-- Equation name is 'LED6', type is output
LED6 = _LC4_C10;
-- Node name is 'LED7'
-- Equation name is 'LED7', type is output
LED7 = _LC6_C12;
-- Node name is 'LED8'
-- Equation name is 'LED8', type is output
LED8 = _LC5_C14;
-- Node name is 'LED9'
-- Equation name is 'LED9', type is output
LED9 = _LC6_C16;
-- Node name is 'LED10'
-- Equation name is 'LED10', type is output
LED10 = _LC3_C16;
-- Node name is 'LED11'
-- Equation name is 'LED11', type is output
LED11 = _LC2_C17;
-- Node name is 'LED12'
-- Equation name is 'LED12', type is output
LED12 = _LC4_C17;
-- Node name is 'LED13'
-- Equation name is 'LED13', type is output
LED13 = _LC1_C20;
-- Node name is 'LED14'
-- Equation name is 'LED14', type is output
LED14 = _LC5_C21;
-- Node name is 'LED15'
-- Equation name is 'LED15', type is output
LED15 = _LC6_C14;
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