📄 xskz.rpt
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-- Node name is ':36' = 'FLOWER22'
-- Equation name is 'FLOWER22', location is LC7_C3, type is buried.
FLOWER22 = DFFE( _EQ024, GLOBAL( CLK), VCC, VCC, !_LC3_C13);
_EQ024 = !CURRENT_STATE~10 & _LC6_C15
# CURRENT_STATE~9 & !CURRENT_STATE~10;
-- Node name is ':35' = 'FLOWER23'
-- Equation name is 'FLOWER23', location is LC3_C3, type is buried.
FLOWER23 = DFFE( _EQ025, GLOBAL( CLK), VCC, VCC, !_LC3_C13);
_EQ025 = !CURRENT_STATE~9 & !CURRENT_STATE~10 & _LC6_C15;
-- Node name is ':34' = 'FLOWER24'
-- Equation name is 'FLOWER24', location is LC3_C18, type is buried.
FLOWER24 = DFFE( _EQ026, GLOBAL( CLK), VCC, VCC, !_LC3_C13);
_EQ026 = _LC4_C18 & _LC8_C19
# CURRENT_STATE~7 & _LC4_C18;
-- Node name is ':33' = 'FLOWER25'
-- Equation name is 'FLOWER25', location is LC6_C13, type is buried.
FLOWER25 = DFFE( _EQ027, GLOBAL( CLK), VCC, VCC, !_LC3_C13);
_EQ027 = _LC2_C19 & _LC7_C18
# _LC7_C18 & _LC8_C19;
-- Node name is ':32' = 'FLOWER26'
-- Equation name is 'FLOWER26', location is LC7_C13, type is buried.
FLOWER26 = DFFE( _EQ028, GLOBAL( CLK), VCC, VCC, !_LC3_C13);
_EQ028 = !CURRENT_STATE~6 & _LC3_C19 & _LC7_C18;
-- Node name is ':31' = 'FLOWER27'
-- Equation name is 'FLOWER27', location is LC7_C23, type is buried.
FLOWER27 = DFFE( _EQ029, GLOBAL( CLK), VCC, VCC, !_LC3_C13);
_EQ029 = !CURRENT_STATE~5 & !CURRENT_STATE~6 & _LC4_C19;
-- Node name is 'LED0'
-- Equation name is 'LED0', type is output
LED0 = FLOWER0;
-- Node name is 'LED1'
-- Equation name is 'LED1', type is output
LED1 = FLOWER1;
-- Node name is 'LED2'
-- Equation name is 'LED2', type is output
LED2 = FLOWER2;
-- Node name is 'LED3'
-- Equation name is 'LED3', type is output
LED3 = FLOWER3;
-- Node name is 'LED4'
-- Equation name is 'LED4', type is output
LED4 = FLOWER4;
-- Node name is 'LED5'
-- Equation name is 'LED5', type is output
LED5 = FLOWER5;
-- Node name is 'LED6'
-- Equation name is 'LED6', type is output
LED6 = FLOWER6;
-- Node name is 'LED7'
-- Equation name is 'LED7', type is output
LED7 = FLOWER7;
-- Node name is 'LED8'
-- Equation name is 'LED8', type is output
LED8 = FLOWER8;
-- Node name is 'LED9'
-- Equation name is 'LED9', type is output
LED9 = FLOWER9;
-- Node name is 'LED10'
-- Equation name is 'LED10', type is output
LED10 = FLOWER10;
-- Node name is 'LED11'
-- Equation name is 'LED11', type is output
LED11 = FLOWER11;
-- Node name is 'LED12'
-- Equation name is 'LED12', type is output
LED12 = FLOWER12;
-- Node name is 'LED13'
-- Equation name is 'LED13', type is output
LED13 = FLOWER13;
-- Node name is 'LED14'
-- Equation name is 'LED14', type is output
LED14 = FLOWER14;
-- Node name is 'LED15'
-- Equation name is 'LED15', type is output
LED15 = FLOWER15;
-- Node name is 'LED16'
-- Equation name is 'LED16', type is output
LED16 = FLOWER16;
-- Node name is 'LED17'
-- Equation name is 'LED17', type is output
LED17 = FLOWER17;
-- Node name is 'LED18'
-- Equation name is 'LED18', type is output
LED18 = FLOWER18;
-- Node name is 'LED19'
-- Equation name is 'LED19', type is output
LED19 = FLOWER19;
-- Node name is 'LED20'
-- Equation name is 'LED20', type is output
LED20 = FLOWER20;
-- Node name is 'LED21'
-- Equation name is 'LED21', type is output
LED21 = FLOWER21;
-- Node name is 'LED22'
-- Equation name is 'LED22', type is output
LED22 = FLOWER22;
-- Node name is 'LED23'
-- Equation name is 'LED23', type is output
LED23 = FLOWER23;
-- Node name is 'LED24'
-- Equation name is 'LED24', type is output
LED24 = FLOWER24;
-- Node name is 'LED25'
-- Equation name is 'LED25', type is output
LED25 = FLOWER25;
-- Node name is 'LED26'
-- Equation name is 'LED26', type is output
LED26 = FLOWER26;
-- Node name is 'LED27'
-- Equation name is 'LED27', type is output
LED27 = FLOWER27;
-- Node name is '~1034~1'
-- Equation name is '~1034~1', location is LC2_C19, type is buried.
-- synthesized logic cell
_LC2_C19 = LCELL( _EQ030);
_EQ030 = !CURRENT_STATE~2
# CURRENT_STATE~3;
-- Node name is '~1078~1'
-- Equation name is '~1078~1', location is LC4_C19, type is buried.
-- synthesized logic cell
_LC4_C19 = LCELL( _EQ031);
_EQ031 = _LC2_C19 & _LC7_C18
# CURRENT_STATE~4 & _LC7_C18;
-- Node name is ':1110'
-- Equation name is '_LC3_C19', type is buried
_LC3_C19 = LCELL( _EQ032);
_EQ032 = _LC2_C19
# CURRENT_STATE~4
# CURRENT_STATE~5;
-- Node name is '~1142~1'
-- Equation name is '~1142~1', location is LC8_C3, type is buried.
-- synthesized logic cell
!_LC8_C3 = _LC8_C3~NOT;
_LC8_C3~NOT = LCELL( _EQ033);
_EQ033 = CURRENT_STATE~10
# CURRENT_STATE~9;
-- Node name is '~1205~1'
-- Equation name is '~1205~1', location is LC7_C18, type is buried.
-- synthesized logic cell
_LC7_C18 = LCELL( _EQ034);
_EQ034 = !CURRENT_STATE~7 & _LC4_C18;
-- Node name is ':1248'
-- Equation name is '_LC8_C18', type is buried
_LC8_C18 = LCELL( _EQ035);
_EQ035 = _LC8_C19
# CURRENT_STATE~7;
-- Node name is '~1268~1'
-- Equation name is '~1268~1', location is LC4_C18, type is buried.
-- synthesized logic cell
_LC4_C18 = LCELL( _EQ036);
_EQ036 = !CURRENT_STATE~8 & _LC8_C3;
-- Node name is ':1317'
-- Equation name is '_LC6_C15', type is buried
_LC6_C15 = LCELL( _EQ037);
_EQ037 = _LC2_C19
# _LC8_C15;
-- Node name is ':2199'
-- Equation name is '_LC8_C15', type is buried
_LC8_C15 = LCELL( _EQ038);
_EQ038 = _LC8_C18
# CURRENT_STATE~8;
-- Node name is ':2502'
-- Equation name is '_LC8_C19', type is buried
_LC8_C19 = LCELL( _EQ039);
_EQ039 = CURRENT_STATE~5
# CURRENT_STATE~6
# CURRENT_STATE~4;
Project Information f:\caideng\xskz.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:02
Fitter 00:00:02
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:06
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,117K
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