📄 cdkzq.vhd
字号:
-- 整个电路系统的VHDL源程序
--CDKZQ.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CDKZQ IS
PORT(CLK_IN:IN STD_LOGIC;
CLR:IN STD_LOGIC;
CHOSE_KEY:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
LED:OUT STD_LOGIC_VECTOR(27 DOWNTO 0));
END ENTITY CDKZQ;
ARCHITECTURE ART OF CDKZQ IS
COMPONENT SXKZ IS
PORT(CHOSE_KEY:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
CLK_IN:IN STD_LOGIC;
CLR:IN STD_LOGIC;
CLK:OUT STD_LOGIC);
END COMPONENT SXKZ;
COMPONENT XSKZ IS
PORT(CLK:IN STD_LOGIC;
CLR:IN STD_LOGIC;
LED:OUT STD_LOGIC_VECTOR(27 DOWNTO 0));
END COMPONENT XSKZ;
SIGNAL S1:STD_LOGIC;
BEGIN
U1:SXKZ PORT MAP(CHOSE_KEY,CLK_IN,CLR,S1);
U2:XSKZ PORT MAP(S1,CLR,LED);
END ARCHITECTURE ART;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -