sxkz.rpt

彩灯显示控制,五个花样,可独立也可循环显示

-- Node name is ':54' 
-- Equation name is '_LC1_C11', type is buried 
!_LC1_C11 = _LC1_C11~NOT;
_LC1_C11~NOT = LCELL( _EQ012);
  _EQ012 = !CHOSE_KEY1
         # !CHOSE_KEY0;

-- Node name is ':62' 
-- Equation name is '_LC5_C9', type is buried 
!_LC5_C9 = _LC5_C9~NOT;
_LC5_C9~NOT = LCELL( _EQ013);
  _EQ013 = !TEMP0
         #  TEMP1
         #  TEMP3
         #  TEMP2;

-- Node name is ':120' 
-- Equation name is '_LC2_C9', type is buried 
!_LC2_C9 = _LC2_C9~NOT;
_LC2_C9~NOT = LCELL( _EQ014);
  _EQ014 = !TEMP0
         # !TEMP1
         #  TEMP3
         #  TEMP2;

-- Node name is ':178' 
-- Equation name is '_LC2_C4', type is buried 
!_LC2_C4 = _LC2_C4~NOT;
_LC2_C4~NOT = LCELL( _EQ015);
  _EQ015 =  TEMP3
         # !_LC6_C9;

-- Node name is ':236' 
-- Equation name is '_LC6_C12', type is buried 
!_LC6_C12 = _LC6_C12~NOT;
_LC6_C12~NOT = LCELL( _EQ016);
  _EQ016 = !TEMP3
         # !_LC6_C9;

-- Node name is ':298' 
-- Equation name is '_LC4_C12', type is buried 
_LC4_C12 = LCELL( _EQ017);
  _EQ017 =  CLLK & !_LC6_C12
         #  CHOSE_KEY0 &  CHOSE_KEY1 & !CLLK &  _LC6_C12
         # !CHOSE_KEY1 &  CLLK
         # !CHOSE_KEY0 &  CLLK;

-- Node name is ':304' 
-- Equation name is '_LC5_C12', type is buried 
_LC5_C12 = LCELL( _EQ018);
  _EQ018 = !_LC1_C12 &  _LC4_C12
         #  CLLK &  _LC1_C12 & !_LC2_C4
         # !CLLK &  _LC1_C12 &  _LC2_C4;

-- Node name is ':310' 
-- Equation name is '_LC7_C12', type is buried 
_LC7_C12 = LCELL( _EQ019);
  _EQ019 = !_LC2_C12 &  _LC5_C12
         #  CLLK & !_LC2_C9 &  _LC2_C12
         # !CLLK &  _LC2_C9 &  _LC2_C12;

-- Node name is ':325' 
-- Equation name is '_LC5_C4', type is buried 
_LC5_C4  = LCELL( _EQ020);
  _EQ020 =  _LC3_C4
         #  _LC4_C4 & !_LC6_C9 &  TEMP3
         #  _LC4_C4 &  _LC6_C9 & !TEMP3;

-- Node name is '~326~1' 
-- Equation name is '~326~1', location is LC4_C4, type is buried.
-- synthesized logic cell 
_LC4_C4  = LCELL( _EQ021);
  _EQ021 =  _LC1_C12 & !_LC2_C4;

-- Node name is ':327' 
-- Equation name is '_LC3_C4', type is buried 
_LC3_C4  = LCELL( _EQ022);
  _EQ022 =  _LC1_C11 & !_LC1_C12 &  _LC6_C9 & !TEMP3
         # !_LC1_C12 & !_LC6_C9 &  TEMP3
         # !_LC1_C11 & !_LC1_C12 &  TEMP3;

-- Node name is ':329' 
-- Equation name is '_LC6_C4', type is buried 
_LC6_C4  = LCELL( _EQ023);
  _EQ023 = !_LC2_C9 &  _LC2_C12 & !_LC6_C9 &  TEMP3
         # !_LC2_C9 &  _LC2_C12 &  _LC6_C9 & !TEMP3;

-- Node name is '~332~1' 
-- Equation name is '~332~1', location is LC8_C4, type is buried.
-- synthesized logic cell 
_LC8_C4  = LCELL( _EQ024);
  _EQ024 =  _LC3_C12 & !_LC5_C9;

-- Node name is ':333' 
-- Equation name is '_LC7_C4', type is buried 
_LC7_C4  = LCELL( _EQ025);
  _EQ025 = !_LC2_C12 & !_LC3_C12 &  _LC5_C4
         # !_LC3_C12 &  _LC6_C4;

-- Node name is ':337' 
-- Equation name is '_LC3_C9', type is buried 
_LC3_C9  = LCELL( _EQ026);
  _EQ026 =  _LC1_C9 &  _LC1_C11 & !_LC6_C12
         # !_LC1_C11 &  TEMP2;

-- Node name is ':340' 
-- Equation name is '_LC4_C9', type is buried 
_LC4_C9  = LCELL( _EQ027);
  _EQ027 = !_LC1_C12 &  _LC3_C9
         #  _LC1_C9 &  _LC1_C12 & !_LC2_C4;

-- Node name is ':343' 
-- Equation name is '_LC7_C9', type is buried 
_LC7_C9  = LCELL( _EQ028);
  _EQ028 = !_LC2_C12 &  _LC4_C9
         #  _LC1_C9 & !_LC2_C9 &  _LC2_C12;

-- Node name is ':352' 
-- Equation name is '_LC4_C5', type is buried 
_LC4_C5  = LCELL( _EQ029);
  _EQ029 =  _LC1_C11 &  _LC3_C5 & !_LC6_C12
         # !_LC1_C11 &  TEMP1;

-- Node name is ':355' 
-- Equation name is '_LC5_C5', type is buried 
_LC5_C5  = LCELL( _EQ030);
  _EQ030 =  _LC1_C12 & !_LC2_C4 &  _LC3_C5
         # !_LC1_C12 &  _LC4_C5;

-- Node name is ':359' 
-- Equation name is '_LC6_C5', type is buried 
_LC6_C5  = LCELL( _EQ031);
  _EQ031 = !_LC2_C9 &  _LC2_C12 &  _LC3_C5;

-- Node name is ':363' 
-- Equation name is '_LC7_C5', type is buried 
_LC7_C5  = LCELL( _EQ032);
  _EQ032 = !_LC2_C12 & !_LC3_C12 &  _LC5_C5
         # !_LC3_C12 &  _LC6_C5;

-- Node name is '~376~1' 
-- Equation name is '~376~1', location is LC1_C5, type is buried.
-- synthesized logic cell 
!_LC1_C5 = _LC1_C5~NOT;
_LC1_C5~NOT = LCELL( _EQ033);
  _EQ033 = !_LC1_C11 & !_LC1_C12 & !_LC2_C12 & !_LC3_C12;



Project Information                                        f:\caideng\sxkz.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 18,172K