📄 sxkz.rpt
字号:
56 - - - -- INPUT 0 0 0 5 CHOSE_KEY0
124 - - - -- INPUT 0 0 0 5 CHOSE_KEY1
55 - - - -- INPUT G 0 0 0 0 CLK_IN
54 - - - -- INPUT G 0 0 0 0 CLR
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\caideng\sxkz.rpt
sxkz
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
91 - - C -- OUTPUT 0 1 0 0 CLK
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\caideng\sxkz.rpt
sxkz
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - C 09 OR2 ! 0 3 0 6 |LPM_ADD_SUB:77|addcore:adder|:59
- 3 - C 05 OR2 0 2 0 4 |LPM_ADD_SUB:77|addcore:adder|:67
- 1 - C 09 OR2 0 3 0 4 |LPM_ADD_SUB:77|addcore:adder|:68
- 8 - C 12 DFFE + 0 3 1 3 CLLK (:6)
- 1 - C 04 DFFE + 0 3 0 7 TEMP3 (:9)
- 8 - C 09 DFFE + 0 4 0 5 TEMP2 (:10)
- 2 - C 05 DFFE + 0 4 0 6 TEMP1 (:11)
- 8 - C 05 DFFE + 0 1 0 5 TEMP0 (:12)
- 3 - C 12 AND2 2 0 0 7 :39
- 2 - C 12 AND2 2 0 0 7 :44
- 1 - C 12 AND2 2 0 0 6 :49
- 1 - C 11 OR2 ! 2 0 0 4 :54
- 5 - C 09 OR2 ! 0 4 0 4 :62
- 2 - C 09 OR2 ! 0 4 0 4 :120
- 2 - C 04 OR2 ! 0 2 0 4 :178
- 6 - C 12 OR2 ! 0 2 0 3 :236
- 4 - C 12 OR2 2 2 0 1 :298
- 5 - C 12 OR2 0 4 0 1 :304
- 7 - C 12 OR2 0 4 0 1 :310
- 5 - C 04 OR2 0 4 0 1 :325
- 4 - C 04 AND2 s 0 2 0 1 ~326~1
- 3 - C 04 OR2 0 4 0 1 :327
- 6 - C 04 OR2 0 4 0 1 :329
- 8 - C 04 AND2 s 0 2 0 1 ~332~1
- 7 - C 04 OR2 0 4 0 1 :333
- 3 - C 09 OR2 0 4 0 1 :337
- 4 - C 09 OR2 0 4 0 1 :340
- 7 - C 09 OR2 0 4 0 1 :343
- 4 - C 05 OR2 0 4 0 1 :352
- 5 - C 05 OR2 0 4 0 1 :355
- 6 - C 05 AND2 0 3 0 1 :359
- 7 - C 05 OR2 0 4 0 1 :363
- 1 - C 05 AND2 s ! 0 4 0 1 ~376~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\caideng\sxkz.rpt
sxkz
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 1/ 96( 1%) 14/ 48( 29%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\caideng\sxkz.rpt
sxkz
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 5 CLK_IN
Device-Specific Information: f:\caideng\sxkz.rpt
sxkz
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 5 CLR
Device-Specific Information: f:\caideng\sxkz.rpt
sxkz
** EQUATIONS **
CHOSE_KEY0 : INPUT;
CHOSE_KEY1 : INPUT;
CLK_IN : INPUT;
CLR : INPUT;
-- Node name is 'CLK'
-- Equation name is 'CLK', type is output
CLK = CLLK;
-- Node name is ':6' = 'CLLK'
-- Equation name is 'CLLK', location is LC8_C12, type is buried.
CLLK = DFFE( _EQ001, GLOBAL( CLK_IN), GLOBAL(!CLR), VCC, VCC);
_EQ001 = !_LC3_C12 & _LC7_C12
# CLLK & _LC3_C12 & !_LC5_C9
# !CLLK & _LC3_C12 & _LC5_C9;
-- Node name is ':12' = 'TEMP0'
-- Equation name is 'TEMP0', location is LC8_C5, type is buried.
TEMP0 = DFFE( _EQ002, GLOBAL( CLK_IN), GLOBAL(!CLR), VCC, VCC);
_EQ002 = _LC1_C5 & !TEMP0
# !_LC1_C5 & TEMP0;
-- Node name is ':11' = 'TEMP1'
-- Equation name is 'TEMP1', location is LC2_C5, type is buried.
TEMP1 = DFFE( _EQ003, GLOBAL( CLK_IN), GLOBAL(!CLR), VCC, VCC);
_EQ003 = _LC7_C5
# _LC3_C5 & _LC3_C12 & !_LC5_C9;
-- Node name is ':10' = 'TEMP2'
-- Equation name is 'TEMP2', location is LC8_C9, type is buried.
TEMP2 = DFFE( _EQ004, GLOBAL( CLK_IN), GLOBAL(!CLR), VCC, VCC);
_EQ004 = !_LC3_C12 & _LC7_C9
# _LC1_C9 & _LC3_C12 & !_LC5_C9;
-- Node name is ':9' = 'TEMP3'
-- Equation name is 'TEMP3', location is LC1_C4, type is buried.
TEMP3 = DFFE( _EQ005, GLOBAL( CLK_IN), GLOBAL(!CLR), VCC, VCC);
_EQ005 = _LC7_C4
# !_LC6_C9 & _LC8_C4 & TEMP3
# _LC6_C9 & _LC8_C4 & !TEMP3;
-- Node name is '|LPM_ADD_SUB:77|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_C9', type is buried
!_LC6_C9 = _LC6_C9~NOT;
_LC6_C9~NOT = LCELL( _EQ006);
_EQ006 = !TEMP2
# !TEMP0
# !TEMP1;
-- Node name is '|LPM_ADD_SUB:77|addcore:adder|:67' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC3_C5', type is buried
_LC3_C5 = LCELL( _EQ007);
_EQ007 = TEMP0 & !TEMP1
# !TEMP0 & TEMP1;
-- Node name is '|LPM_ADD_SUB:77|addcore:adder|:68' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC1_C9', type is buried
_LC1_C9 = LCELL( _EQ008);
_EQ008 = !TEMP0 & TEMP2
# !TEMP1 & TEMP2
# TEMP0 & TEMP1 & !TEMP2;
-- Node name is ':39'
-- Equation name is '_LC3_C12', type is buried
_LC3_C12 = LCELL( _EQ009);
_EQ009 = !CHOSE_KEY0 & !CHOSE_KEY1;
-- Node name is ':44'
-- Equation name is '_LC2_C12', type is buried
_LC2_C12 = LCELL( _EQ010);
_EQ010 = CHOSE_KEY0 & !CHOSE_KEY1;
-- Node name is ':49'
-- Equation name is '_LC1_C12', type is buried
_LC1_C12 = LCELL( _EQ011);
_EQ011 = !CHOSE_KEY0 & CHOSE_KEY1;
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