multi_cpu_2c35.v

altera的fpga设计

      if (reset_n == 0)
          cpu1_jtag_debug_module_saved_chosen_master_vector <= 0;
      else if (cpu1_jtag_debug_module_allow_new_arb_cycle)
          cpu1_jtag_debug_module_saved_chosen_master_vector <= |cpu1_jtag_debug_module_grant_vector ? cpu1_jtag_debug_module_grant_vector : cpu1_jtag_debug_module_saved_chosen_master_vector;
    end


  //onehot encoding of chosen master
  assign cpu1_jtag_debug_module_grant_vector = {(cpu1_jtag_debug_module_chosen_master_double_vector[1] | cpu1_jtag_debug_module_chosen_master_double_vector[3]),
    (cpu1_jtag_debug_module_chosen_master_double_vector[0] | cpu1_jtag_debug_module_chosen_master_double_vector[2])};

  //cpu1/jtag_debug_module chosen master rotated left, which is an e_assign
  assign cpu1_jtag_debug_module_chosen_master_rot_left = (cpu1_jtag_debug_module_arb_winner << 1) ? (cpu1_jtag_debug_module_arb_winner << 1) : 1;

  //cpu1/jtag_debug_module's addend for next-master-grant
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu1_jtag_debug_module_arb_addend <= 1;
      else if (|cpu1_jtag_debug_module_grant_vector)
          cpu1_jtag_debug_module_arb_addend <= cpu1_jtag_debug_module_end_xfer? cpu1_jtag_debug_module_chosen_master_rot_left : cpu1_jtag_debug_module_grant_vector;
    end


  assign cpu1_jtag_debug_module_begintransfer = cpu1_jtag_debug_module_begins_xfer;
  //assign lhs ~cpu1_jtag_debug_module_reset of type reset_n to cpu1_jtag_debug_module_reset_n, which is an e_assign
  assign cpu1_jtag_debug_module_reset = ~cpu1_jtag_debug_module_reset_n;

  //cpu1_jtag_debug_module_reset_n assignment, which is an e_assign
  assign cpu1_jtag_debug_module_reset_n = reset_n;

  //assign cpu1_jtag_debug_module_resetrequest_from_sa = cpu1_jtag_debug_module_resetrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign cpu1_jtag_debug_module_resetrequest_from_sa = cpu1_jtag_debug_module_resetrequest;

  assign cpu1_jtag_debug_module_chipselect = cpu1_data_master_granted_cpu1_jtag_debug_module | cpu1_instruction_master_granted_cpu1_jtag_debug_module;
  //cpu1_jtag_debug_module_firsttransfer first transaction, which is an e_assign
  assign cpu1_jtag_debug_module_firsttransfer = ~(cpu1_jtag_debug_module_slavearbiterlockenable & cpu1_jtag_debug_module_any_continuerequest);

  //cpu1_jtag_debug_module_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign cpu1_jtag_debug_module_beginbursttransfer_internal = cpu1_jtag_debug_module_begins_xfer & cpu1_jtag_debug_module_firsttransfer;

  //cpu1_jtag_debug_module_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign cpu1_jtag_debug_module_arbitration_holdoff_internal = cpu1_jtag_debug_module_begins_xfer & cpu1_jtag_debug_module_firsttransfer;

  //cpu1_jtag_debug_module_write assignment, which is an e_mux
  assign cpu1_jtag_debug_module_write = cpu1_data_master_granted_cpu1_jtag_debug_module & cpu1_data_master_write;

  //cpu1_jtag_debug_module_address mux, which is an e_mux
  assign cpu1_jtag_debug_module_address = (cpu1_data_master_granted_cpu1_jtag_debug_module)? (cpu1_data_master_address_to_slave >> 2) :
    (cpu1_instruction_master_address_to_slave >> 2);

  //d1_cpu1_jtag_debug_module_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_cpu1_jtag_debug_module_end_xfer <= 1;
      else if (1)
          d1_cpu1_jtag_debug_module_end_xfer <= cpu1_jtag_debug_module_end_xfer;
    end


  //cpu1_jtag_debug_module_waits_for_read in a cycle, which is an e_mux
  assign cpu1_jtag_debug_module_waits_for_read = cpu1_jtag_debug_module_in_a_read_cycle & cpu1_jtag_debug_module_begins_xfer;

  //cpu1_jtag_debug_module_in_a_read_cycle assignment, which is an e_assign
  assign cpu1_jtag_debug_module_in_a_read_cycle = (cpu1_data_master_granted_cpu1_jtag_debug_module & cpu1_data_master_read) | (cpu1_instruction_master_granted_cpu1_jtag_debug_module & cpu1_instruction_master_read);

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = cpu1_jtag_debug_module_in_a_read_cycle;

  //cpu1_jtag_debug_module_waits_for_write in a cycle, which is an e_mux
  assign cpu1_jtag_debug_module_waits_for_write = cpu1_jtag_debug_module_in_a_write_cycle & cpu1_jtag_debug_module_begins_xfer;

  //cpu1_jtag_debug_module_in_a_write_cycle assignment, which is an e_assign
  assign cpu1_jtag_debug_module_in_a_write_cycle = cpu1_data_master_granted_cpu1_jtag_debug_module & cpu1_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = cpu1_jtag_debug_module_in_a_write_cycle;

  assign wait_for_cpu1_jtag_debug_module_counter = 0;
  //cpu1_jtag_debug_module_byteenable byte enable port mux, which is an e_mux
  assign cpu1_jtag_debug_module_byteenable = (cpu1_data_master_granted_cpu1_jtag_debug_module)? cpu1_data_master_byteenable :
    -1;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu1_data_master_granted_cpu1_jtag_debug_module + cpu1_instruction_master_granted_cpu1_jtag_debug_module > 1)
        begin
          $write("%0d ns: > 1 of grant signals are active simultaneously", $time);
          $stop;
        end
    end


  //saved_grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu1_data_master_saved_grant_cpu1_jtag_debug_module + cpu1_instruction_master_saved_grant_cpu1_jtag_debug_module > 1)
        begin
          $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu1_data_master_arbitrator (
                                     // inputs:
                                      button_pio_s1_irq_from_sa,
                                      button_pio_s1_readdata_from_sa,
                                      clk,
                                      clock_0_in_readdata_from_sa,
                                      clock_0_in_waitrequest_from_sa,
                                      cpu1_data_master_address,
                                      cpu1_data_master_byteenable_ext_flash_s1,
                                      cpu1_data_master_debugaccess,
                                      cpu1_data_master_granted_button_pio_s1,
                                      cpu1_data_master_granted_clock_0_in,
                                      cpu1_data_master_granted_cpu1_jtag_debug_module,
                                      cpu1_data_master_granted_cpu1_timer_s1,
                                      cpu1_data_master_granted_ddr_sdram_s1,
                                      cpu1_data_master_granted_ext_flash_s1,
                                      cpu1_data_master_granted_ext_ssram_s1,
                                      cpu1_data_master_granted_jtag_uart_avalon_jtag_slave,
                                      cpu1_data_master_granted_led_pio_s1,
                                      cpu1_data_master_granted_message_buffer_mutex_s1,
                                      cpu1_data_master_granted_message_buffer_ram_s1,
                                      cpu1_data_master_granted_sysid_control_slave,
                                      cpu1_data_master_qualified_request_button_pio_s1,
                                      cpu1_data_master_qualified_request_clock_0_in,
                                      cpu1_data_master_qualified_request_cpu1_jtag_debug_module,
                                      cpu1_data_master_qualified_request_cpu1_timer_s1,
                                      cpu1_data_master_qualified_request_ddr_sdram_s1,
                                      cpu1_data_master_qualified_request_ext_flash_s1,
                                      cpu1_data_master_qualified_request_ext_ssram_s1,
                                      cpu1_data_master_qualified_request_jtag_uart_avalon_jtag_slave,
                                      cpu1_data_master_qualified_request_led_pio_s1,
                                      cpu1_data_master_qualified_request_message_buffer_mutex_s1,
                                      cpu1_data_master_qualified_request_message_buffer_ram_s1,
                                      cpu1_data_master_qualified_request_sysid_control_slave,
                                      cpu1_data_master_read,
                                      cpu1_data_master_read_data_valid_button_pio_s1,
                                      cpu1_data_master_read_data_valid_clock_0_in,
                                      cpu1_data_master_read_data_valid_cpu1_jtag_debug_module,
                                      cpu1_data_master_read_data_valid_cpu1_timer_s1,
                                      cpu1_data_master_read_data_valid_ddr_sdram_s1,
                                      cpu1_data_master_read_data_valid_ddr_sdram_s1_shift_register,
                                      cpu1_data_master_read_data_valid_ext_flash_s1,
                                      cpu1_data_master_read_data_valid_ext_ssram_s1,
                                      cpu1_data_master_read_data_valid_jtag_uart_avalon_jtag_slave,
                                      cpu1_data_master_read_data_valid_led_pio_s1,
                                      cpu1_data_master_read_data_valid_message_buffer_mutex_s1,
                                      cpu1_data_master_read_data_valid_message_buffer_ram_s1,
                                      cpu1_data_master_read_data_valid_sysid_control_slave,
                                      cpu1_data_master_requests_button_pio_s1,
                                      cpu1_data_master_requests_clock_0_in,
                                      cpu1_data_master_requests_cpu1_jtag_debug_module,
                                      cpu1_data_master_requests_cpu1_timer_s1,
                                      cpu1_data_master_requests_ddr_sdram_s1,
                                      cpu1_data_master_requests_ext_flash_s1,
                                      cpu1_data_master_requests_ext_ssram_s1,
                                      cpu1_data_master_requests_jtag_uart_avalon_jtag_slave,
                                      cpu1_data_master_requests_led_pio_s1,
                                      cpu1_data_master_requests_message_buffer_mutex_s1,
                                      cpu1_data_master_requests_message_buffer_ram_s1,
                                      cpu1_data_master_requests_sysid_control_slave,
                                      cpu1_data_master_write,
                                      cpu1_data_master_writedata,
                                      cpu1_jtag_debug_module_readdata_from_sa,
                                      cpu1_timer_s1_irq_from_sa,
                                      cpu1_timer_s1_readdata_from_sa,
                                      d1_button_pio_s1_end_xfer,
                                      d1_clock_0_in_end_xfer,
                                      d1_cpu1_jtag_debug_module_end_xfer,
                                      d1_cpu1_timer_s1_end_xfer,
                                      d1_ddr_sdram_s1_end_xfer,
                                      d1_ext_flash_enet_bus_avalon_slave_end_xfer,
                                      d1_ext_ssram_bus_avalon_slave_end_xfer,
                                      d1_jtag_uart_avalon_jtag_slave_end_xfer,
                                      d1_led_pio_s1_end_xfer,
                                      d1_message_buffer_mutex_s1_end_xfer,
                                      d1_message_buffer_ram_s1_end_xfer,
                                      d1_sysid_control_slave_end_xfer,
                                      ddr_sdram_s1_readdata_from_sa,
                                      ddr_sdram_s1_waitrequest_n_from_sa,
                                      ext_flash_s1_wait_counter_eq_0,
                                      ext_flash_s1_wait_counter_eq_1,
                                      incoming_data_to_and_from_the_ext_ssram,
                                      incoming_ext_flash_enet_bus_data_with_Xs_converted_to_0,
                                      jtag_uart_avalon_jtag_slave_irq_from_sa,
                                      jtag_uart_avalon_jtag_slave_readdata_from_sa,
                                      jtag_uart_avalon_jtag_slave_waitrequest_from_sa,
                                      message_buffer_mutex_s1_readdata_from_sa,
                                      message_buffer_ram_s1_readdata_from_sa,
                                      registered_cpu1_data_master_read_data_valid_ext_flash_s1,
                                      registered_cpu1_data_master_read_data_valid_ext_ssram_s1,
                                      registered_cpu1_data_master_read_data_valid_message_buffer_ram_s1,
                                      reset_n,
                                      sysid_control_slave_readdata_from_sa,

                                     // outputs:
                                      cpu1_data_master_address_to_slave,
                                      cpu1_data_master_dbs_address,
                                      cpu1_data_master_dbs_write_8,
                                      cpu1_data_master_irq,
                                      cpu1_data_master_no_byte_enables_and_last_term,
                                      cpu1_data_master_readdata,
                                      cpu1_data_master_waitrequest
                                   )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output  [ 26: 0] cpu1_data_master_address_to_slave;
  output  [  1: 0] cpu1_data_master_dbs_address;
  output  [  7: 0] cpu1_data_master_dbs_write_8;
  output  [ 31: 0] cpu1_data_master_irq;
  output           cpu1_data_master_no_byte_enables_and_last_term;
  output  [ 31: 0] cpu1_data_master_readdata;
  output           cpu1_data_master_waitrequest;
  input            button_pio_s1_irq_from_sa;
  input   [  3: 0] button_pio_s1_readdata_from_sa;
  input            clk;
  input   [ 15: 0] clock_0_in_readdata_from_sa;
  input            clock_0_in_waitrequest_from_sa;
  input   [ 26: 0] cpu1_data_master_address;
  input            cpu1_data_master_byteenable_ext_flash_s1;
  in