multi_cpu_2c35.v

altera的fpga设计

                                            d1_cpu1_jtag_debug_module_end_xfer
                                         )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output           cpu1_data_master_granted_cpu1_jtag_debug_module;
  output           cpu1_data_master_qualified_request_cpu1_jtag_debug_module;
  output           cpu1_data_master_read_data_valid_cpu1_jtag_debug_module;
  output           cpu1_data_master_requests_cpu1_jtag_debug_module;
  output           cpu1_instruction_master_granted_cpu1_jtag_debug_module;
  output           cpu1_instruction_master_qualified_request_cpu1_jtag_debug_module;
  output           cpu1_instruction_master_read_data_valid_cpu1_jtag_debug_module;
  output           cpu1_instruction_master_requests_cpu1_jtag_debug_module;
  output  [  8: 0] cpu1_jtag_debug_module_address;
  output           cpu1_jtag_debug_module_begintransfer;
  output  [  3: 0] cpu1_jtag_debug_module_byteenable;
  output           cpu1_jtag_debug_module_chipselect;
  output           cpu1_jtag_debug_module_debugaccess;
  output  [ 31: 0] cpu1_jtag_debug_module_readdata_from_sa;
  output           cpu1_jtag_debug_module_reset;
  output           cpu1_jtag_debug_module_reset_n;
  output           cpu1_jtag_debug_module_resetrequest_from_sa;
  output           cpu1_jtag_debug_module_write;
  output  [ 31: 0] cpu1_jtag_debug_module_writedata;
  output           d1_cpu1_jtag_debug_module_end_xfer;
  input            clk;
  input   [ 26: 0] cpu1_data_master_address_to_slave;
  input   [  3: 0] cpu1_data_master_byteenable;
  input            cpu1_data_master_debugaccess;
  input            cpu1_data_master_read;
  input            cpu1_data_master_write;
  input   [ 31: 0] cpu1_data_master_writedata;
  input   [ 26: 0] cpu1_instruction_master_address_to_slave;
  input   [  1: 0] cpu1_instruction_master_latency_counter;
  input            cpu1_instruction_master_read;
  input            cpu1_instruction_master_read_data_valid_ddr_sdram_s1_shift_register;
  input   [ 31: 0] cpu1_jtag_debug_module_readdata;
  input            cpu1_jtag_debug_module_resetrequest;
  input            reset_n;

  wire             cpu1_data_master_arbiterlock;
  wire             cpu1_data_master_arbiterlock2;
  wire             cpu1_data_master_continuerequest;
  wire             cpu1_data_master_granted_cpu1_jtag_debug_module;
  wire             cpu1_data_master_qualified_request_cpu1_jtag_debug_module;
  wire             cpu1_data_master_read_data_valid_cpu1_jtag_debug_module;
  wire             cpu1_data_master_requests_cpu1_jtag_debug_module;
  wire             cpu1_data_master_saved_grant_cpu1_jtag_debug_module;
  wire             cpu1_instruction_master_arbiterlock;
  wire             cpu1_instruction_master_arbiterlock2;
  wire             cpu1_instruction_master_continuerequest;
  wire             cpu1_instruction_master_granted_cpu1_jtag_debug_module;
  wire             cpu1_instruction_master_qualified_request_cpu1_jtag_debug_module;
  wire             cpu1_instruction_master_read_data_valid_cpu1_jtag_debug_module;
  wire             cpu1_instruction_master_requests_cpu1_jtag_debug_module;
  wire             cpu1_instruction_master_saved_grant_cpu1_jtag_debug_module;
  wire    [  8: 0] cpu1_jtag_debug_module_address;
  wire             cpu1_jtag_debug_module_allgrants;
  wire             cpu1_jtag_debug_module_allow_new_arb_cycle;
  wire             cpu1_jtag_debug_module_any_continuerequest;
  reg     [  1: 0] cpu1_jtag_debug_module_arb_addend;
  wire             cpu1_jtag_debug_module_arb_counter_enable;
  reg     [  2: 0] cpu1_jtag_debug_module_arb_share_counter;
  wire    [  2: 0] cpu1_jtag_debug_module_arb_share_counter_next_value;
  wire    [  2: 0] cpu1_jtag_debug_module_arb_share_set_values;
  wire    [  1: 0] cpu1_jtag_debug_module_arb_winner;
  wire             cpu1_jtag_debug_module_arbitration_holdoff_internal;
  wire             cpu1_jtag_debug_module_beginbursttransfer_internal;
  wire             cpu1_jtag_debug_module_begins_xfer;
  wire             cpu1_jtag_debug_module_begintransfer;
  wire    [  3: 0] cpu1_jtag_debug_module_byteenable;
  wire             cpu1_jtag_debug_module_chipselect;
  wire    [  3: 0] cpu1_jtag_debug_module_chosen_master_double_vector;
  wire    [  1: 0] cpu1_jtag_debug_module_chosen_master_rot_left;
  wire             cpu1_jtag_debug_module_debugaccess;
  wire             cpu1_jtag_debug_module_end_xfer;
  wire             cpu1_jtag_debug_module_firsttransfer;
  wire    [  1: 0] cpu1_jtag_debug_module_grant_vector;
  wire             cpu1_jtag_debug_module_in_a_read_cycle;
  wire             cpu1_jtag_debug_module_in_a_write_cycle;
  wire    [  1: 0] cpu1_jtag_debug_module_master_qreq_vector;
  wire             cpu1_jtag_debug_module_non_bursting_master_requests;
  wire    [ 31: 0] cpu1_jtag_debug_module_readdata_from_sa;
  wire             cpu1_jtag_debug_module_reset;
  wire             cpu1_jtag_debug_module_reset_n;
  wire             cpu1_jtag_debug_module_resetrequest_from_sa;
  reg     [  1: 0] cpu1_jtag_debug_module_saved_chosen_master_vector;
  reg              cpu1_jtag_debug_module_slavearbiterlockenable;
  wire             cpu1_jtag_debug_module_slavearbiterlockenable2;
  wire             cpu1_jtag_debug_module_waits_for_read;
  wire             cpu1_jtag_debug_module_waits_for_write;
  wire             cpu1_jtag_debug_module_write;
  wire    [ 31: 0] cpu1_jtag_debug_module_writedata;
  reg              d1_cpu1_jtag_debug_module_end_xfer;
  reg              d1_reasons_to_wait;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  reg              last_cycle_cpu1_data_master_granted_slave_cpu1_jtag_debug_module;
  reg              last_cycle_cpu1_instruction_master_granted_slave_cpu1_jtag_debug_module;
  wire             wait_for_cpu1_jtag_debug_module_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~cpu1_jtag_debug_module_end_xfer;
    end


  assign cpu1_jtag_debug_module_begins_xfer = ~d1_reasons_to_wait & ((cpu1_data_master_qualified_request_cpu1_jtag_debug_module | cpu1_instruction_master_qualified_request_cpu1_jtag_debug_module));
  //assign cpu1_jtag_debug_module_readdata_from_sa = cpu1_jtag_debug_module_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign cpu1_jtag_debug_module_readdata_from_sa = cpu1_jtag_debug_module_readdata;

  assign cpu1_data_master_requests_cpu1_jtag_debug_module = ({cpu1_data_master_address_to_slave[26 : 11] , 11'b0} == 27'h1010000) & (cpu1_data_master_read | cpu1_data_master_write);
  //cpu1_jtag_debug_module_arb_share_counter set values, which is an e_mux
  assign cpu1_jtag_debug_module_arb_share_set_values = 1;

  //cpu1_jtag_debug_module_non_bursting_master_requests mux, which is an e_mux
  assign cpu1_jtag_debug_module_non_bursting_master_requests = cpu1_data_master_requests_cpu1_jtag_debug_module |
    cpu1_instruction_master_requests_cpu1_jtag_debug_module |
    cpu1_data_master_requests_cpu1_jtag_debug_module |
    cpu1_instruction_master_requests_cpu1_jtag_debug_module;

  //cpu1_jtag_debug_module_arb_share_counter_next_value assignment, which is an e_assign
  assign cpu1_jtag_debug_module_arb_share_counter_next_value = cpu1_jtag_debug_module_firsttransfer ? (cpu1_jtag_debug_module_arb_share_set_values - 1) : |cpu1_jtag_debug_module_arb_share_counter ? (cpu1_jtag_debug_module_arb_share_counter - 1) : 0;

  //cpu1_jtag_debug_module_allgrants all slave grants, which is an e_mux
  assign cpu1_jtag_debug_module_allgrants = |cpu1_jtag_debug_module_grant_vector |
    |cpu1_jtag_debug_module_grant_vector |
    |cpu1_jtag_debug_module_grant_vector |
    |cpu1_jtag_debug_module_grant_vector;

  //cpu1_jtag_debug_module_end_xfer assignment, which is an e_assign
  assign cpu1_jtag_debug_module_end_xfer = ~(cpu1_jtag_debug_module_waits_for_read | cpu1_jtag_debug_module_waits_for_write);

  //cpu1_jtag_debug_module_arb_share_counter arbitration counter enable, which is an e_assign
  assign cpu1_jtag_debug_module_arb_counter_enable = (cpu1_jtag_debug_module_end_xfer & cpu1_jtag_debug_module_allgrants) | (cpu1_jtag_debug_module_end_xfer & ~cpu1_jtag_debug_module_non_bursting_master_requests);

  //cpu1_jtag_debug_module_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu1_jtag_debug_module_arb_share_counter <= 0;
      else if (cpu1_jtag_debug_module_arb_counter_enable)
          cpu1_jtag_debug_module_arb_share_counter <= cpu1_jtag_debug_module_arb_share_counter_next_value;
    end


  //cpu1_jtag_debug_module_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu1_jtag_debug_module_slavearbiterlockenable <= 0;
      else if ((|cpu1_jtag_debug_module_master_qreq_vector & cpu1_jtag_debug_module_end_xfer) | (cpu1_jtag_debug_module_end_xfer & ~cpu1_jtag_debug_module_non_bursting_master_requests))
          cpu1_jtag_debug_module_slavearbiterlockenable <= |cpu1_jtag_debug_module_arb_share_counter_next_value;
    end


  //cpu1/data_master cpu1/jtag_debug_module arbiterlock, which is an e_assign
  assign cpu1_data_master_arbiterlock = cpu1_jtag_debug_module_slavearbiterlockenable & cpu1_data_master_continuerequest;

  //cpu1_jtag_debug_module_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign cpu1_jtag_debug_module_slavearbiterlockenable2 = |cpu1_jtag_debug_module_arb_share_counter_next_value;

  //cpu1/data_master cpu1/jtag_debug_module arbiterlock2, which is an e_assign
  assign cpu1_data_master_arbiterlock2 = cpu1_jtag_debug_module_slavearbiterlockenable2 & cpu1_data_master_continuerequest;

  //cpu1/instruction_master cpu1/jtag_debug_module arbiterlock, which is an e_assign
  assign cpu1_instruction_master_arbiterlock = cpu1_jtag_debug_module_slavearbiterlockenable & cpu1_instruction_master_continuerequest;

  //cpu1/instruction_master cpu1/jtag_debug_module arbiterlock2, which is an e_assign
  assign cpu1_instruction_master_arbiterlock2 = cpu1_jtag_debug_module_slavearbiterlockenable2 & cpu1_instruction_master_continuerequest;

  //cpu1/instruction_master granted cpu1/jtag_debug_module last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu1_instruction_master_granted_slave_cpu1_jtag_debug_module <= 0;
      else if (1)
          last_cycle_cpu1_instruction_master_granted_slave_cpu1_jtag_debug_module <= cpu1_instruction_master_saved_grant_cpu1_jtag_debug_module ? 1 : (cpu1_jtag_debug_module_arbitration_holdoff_internal | ~cpu1_instruction_master_requests_cpu1_jtag_debug_module) ? 0 : last_cycle_cpu1_instruction_master_granted_slave_cpu1_jtag_debug_module;
    end


  //cpu1_instruction_master_continuerequest continued request, which is an e_mux
  assign cpu1_instruction_master_continuerequest = last_cycle_cpu1_instruction_master_granted_slave_cpu1_jtag_debug_module & cpu1_instruction_master_requests_cpu1_jtag_debug_module;

  //cpu1_jtag_debug_module_any_continuerequest at least one master continues requesting, which is an e_mux
  assign cpu1_jtag_debug_module_any_continuerequest = cpu1_instruction_master_continuerequest |
    cpu1_data_master_continuerequest;

  assign cpu1_data_master_qualified_request_cpu1_jtag_debug_module = cpu1_data_master_requests_cpu1_jtag_debug_module & ~(cpu1_instruction_master_arbiterlock);
  //cpu1_jtag_debug_module_writedata mux, which is an e_mux
  assign cpu1_jtag_debug_module_writedata = cpu1_data_master_writedata;

  //mux cpu1_jtag_debug_module_debugaccess, which is an e_mux
  assign cpu1_jtag_debug_module_debugaccess = cpu1_data_master_debugaccess;

  assign cpu1_instruction_master_requests_cpu1_jtag_debug_module = (({cpu1_instruction_master_address_to_slave[26 : 11] , 11'b0} == 27'h1010000) & (cpu1_instruction_master_read)) & cpu1_instruction_master_read;
  //cpu1/data_master granted cpu1/jtag_debug_module last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu1_data_master_granted_slave_cpu1_jtag_debug_module <= 0;
      else if (1)
          last_cycle_cpu1_data_master_granted_slave_cpu1_jtag_debug_module <= cpu1_data_master_saved_grant_cpu1_jtag_debug_module ? 1 : (cpu1_jtag_debug_module_arbitration_holdoff_internal | ~cpu1_data_master_requests_cpu1_jtag_debug_module) ? 0 : last_cycle_cpu1_data_master_granted_slave_cpu1_jtag_debug_module;
    end


  //cpu1_data_master_continuerequest continued request, which is an e_mux
  assign cpu1_data_master_continuerequest = last_cycle_cpu1_data_master_granted_slave_cpu1_jtag_debug_module & cpu1_data_master_requests_cpu1_jtag_debug_module;

  assign cpu1_instruction_master_qualified_request_cpu1_jtag_debug_module = cpu1_instruction_master_requests_cpu1_jtag_debug_module & ~((cpu1_instruction_master_read & ((cpu1_instruction_master_latency_counter != 0) | (|cpu1_instruction_master_read_data_valid_ddr_sdram_s1_shift_register))) | cpu1_data_master_arbiterlock);
  //local readdatavalid cpu1_instruction_master_read_data_valid_cpu1_jtag_debug_module, which is an e_mux
  assign cpu1_instruction_master_read_data_valid_cpu1_jtag_debug_module = cpu1_instruction_master_granted_cpu1_jtag_debug_module & cpu1_instruction_master_read & ~cpu1_jtag_debug_module_waits_for_read;

  //allow new arb cycle for cpu1/jtag_debug_module, which is an e_assign
  assign cpu1_jtag_debug_module_allow_new_arb_cycle = ~cpu1_data_master_arbiterlock & ~cpu1_instruction_master_arbiterlock;

  //cpu1/instruction_master assignment into master qualified-requests vector for cpu1/jtag_debug_module, which is an e_assign
  assign cpu1_jtag_debug_module_master_qreq_vector[0] = cpu1_instruction_master_qualified_request_cpu1_jtag_debug_module;

  //cpu1/instruction_master grant cpu1/jtag_debug_module, which is an e_assign
  assign cpu1_instruction_master_granted_cpu1_jtag_debug_module = cpu1_jtag_debug_module_grant_vector[0];

  //cpu1/instruction_master saved-grant cpu1/jtag_debug_module, which is an e_assign
  assign cpu1_instruction_master_saved_grant_cpu1_jtag_debug_module = cpu1_jtag_debug_module_arb_winner[0] && cpu1_instruction_master_requests_cpu1_jtag_debug_module;

  //cpu1/data_master assignment into master qualified-requests vector for cpu1/jtag_debug_module, which is an e_assign
  assign cpu1_jtag_debug_module_master_qreq_vector[1] = cpu1_data_master_qualified_request_cpu1_jtag_debug_module;

  //cpu1/data_master grant cpu1/jtag_debug_module, which is an e_assign
  assign cpu1_data_master_granted_cpu1_jtag_debug_module = cpu1_jtag_debug_module_grant_vector[1];

  //cpu1/data_master saved-grant cpu1/jtag_debug_module, which is an e_assign
  assign cpu1_data_master_saved_grant_cpu1_jtag_debug_module = cpu1_jtag_debug_module_arb_winner[1] && cpu1_data_master_requests_cpu1_jtag_debug_module;

  //cpu1/jtag_debug_module chosen-master double-vector, which is an e_assign
  assign cpu1_jtag_debug_module_chosen_master_double_vector = {cpu1_jtag_debug_module_master_qreq_vector, cpu1_jtag_debug_module_master_qreq_vector} & ({~cpu1_jtag_debug_module_master_qreq_vector, ~cpu1_jtag_debug_module_master_qreq_vector} + cpu1_jtag_debug_module_arb_addend);

  //stable onehot encoding of arb winner
  assign cpu1_jtag_debug_module_arb_winner = (cpu1_jtag_debug_module_allow_new_arb_cycle & | cpu1_jtag_debug_module_grant_vector) ? cpu1_jtag_debug_module_grant_vector : cpu1_jtag_debug_module_saved_chosen_master_vector;

  //saved cpu1_jtag_debug_module_grant_vector, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin