multi_cpu_2c35.v

altera的fpga设计

  assign clock_0_in_in_a_read_cycle = cpu1_data_master_granted_clock_0_in & cpu1_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = clock_0_in_in_a_read_cycle;

  //clock_0_in_waits_for_write in a cycle, which is an e_mux
  assign clock_0_in_waits_for_write = clock_0_in_in_a_write_cycle & clock_0_in_waitrequest_from_sa;

  //clock_0_in_in_a_write_cycle assignment, which is an e_assign
  assign clock_0_in_in_a_write_cycle = cpu1_data_master_granted_clock_0_in & cpu1_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = clock_0_in_in_a_write_cycle;

  assign wait_for_clock_0_in_counter = 0;
  //clock_0_in_byteenable byte enable port mux, which is an e_mux
  assign clock_0_in_byteenable = (cpu1_data_master_granted_clock_0_in)? cpu1_data_master_byteenable :
    -1;


endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module clock_0_out_arbitrator (
                                // inputs:
                                 clk,
                                 clock_0_out_address,
                                 clock_0_out_granted_pll_s1,
                                 clock_0_out_qualified_request_pll_s1,
                                 clock_0_out_read,
                                 clock_0_out_read_data_valid_pll_s1,
                                 clock_0_out_requests_pll_s1,
                                 clock_0_out_write,
                                 clock_0_out_writedata,
                                 d1_pll_s1_end_xfer,
                                 pll_s1_readdata_from_sa,
                                 reset_n,

                                // outputs:
                                 clock_0_out_address_to_slave,
                                 clock_0_out_readdata,
                                 clock_0_out_reset_n,
                                 clock_0_out_waitrequest
                              )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output  [  3: 0] clock_0_out_address_to_slave;
  output  [ 15: 0] clock_0_out_readdata;
  output           clock_0_out_reset_n;
  output           clock_0_out_waitrequest;
  input            clk;
  input   [  3: 0] clock_0_out_address;
  input            clock_0_out_granted_pll_s1;
  input            clock_0_out_qualified_request_pll_s1;
  input            clock_0_out_read;
  input            clock_0_out_read_data_valid_pll_s1;
  input            clock_0_out_requests_pll_s1;
  input            clock_0_out_write;
  input   [ 15: 0] clock_0_out_writedata;
  input            d1_pll_s1_end_xfer;
  input   [ 15: 0] pll_s1_readdata_from_sa;
  input            reset_n;

  reg              active_and_waiting_last_time;
  reg     [  3: 0] clock_0_out_address_last_time;
  wire    [  3: 0] clock_0_out_address_to_slave;
  reg              clock_0_out_read_last_time;
  wire    [ 15: 0] clock_0_out_readdata;
  wire             clock_0_out_reset_n;
  wire             clock_0_out_run;
  wire             clock_0_out_waitrequest;
  reg              clock_0_out_write_last_time;
  reg     [ 15: 0] clock_0_out_writedata_last_time;
  wire             r_2;
  //r_2 master_run cascaded wait assignment, which is an e_assign
  assign r_2 = 1 & ((~clock_0_out_qualified_request_pll_s1 | ~clock_0_out_read | (1 & ~d1_pll_s1_end_xfer & clock_0_out_read))) & ((~clock_0_out_qualified_request_pll_s1 | ~clock_0_out_write | (1 & clock_0_out_write)));

  //cascaded wait assignment, which is an e_assign
  assign clock_0_out_run = r_2;

  //optimize select-logic by passing only those address bits which matter.
  assign clock_0_out_address_to_slave = clock_0_out_address;

  //clock_0/out readdata mux, which is an e_mux
  assign clock_0_out_readdata = pll_s1_readdata_from_sa;

  //actual waitrequest port, which is an e_assign
  assign clock_0_out_waitrequest = ~clock_0_out_run;

  //clock_0_out_reset_n assignment, which is an e_assign
  assign clock_0_out_reset_n = reset_n;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //clock_0_out_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          clock_0_out_address_last_time <= 0;
      else if (1)
          clock_0_out_address_last_time <= clock_0_out_address;
    end


  //clock_0/out waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else if (1)
          active_and_waiting_last_time <= clock_0_out_waitrequest & (clock_0_out_read | clock_0_out_write);
    end


  //clock_0_out_address matches last port_name, which is an e_process
  always @(active_and_waiting_last_time or clock_0_out_address or clock_0_out_address_last_time)
    begin
      if (active_and_waiting_last_time & (clock_0_out_address != clock_0_out_address_last_time))
        begin
          $write("%0d ns: clock_0_out_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //clock_0_out_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          clock_0_out_read_last_time <= 0;
      else if (1)
          clock_0_out_read_last_time <= clock_0_out_read;
    end


  //clock_0_out_read matches last port_name, which is an e_process
  always @(active_and_waiting_last_time or clock_0_out_read or clock_0_out_read_last_time)
    begin
      if (active_and_waiting_last_time & (clock_0_out_read != clock_0_out_read_last_time))
        begin
          $write("%0d ns: clock_0_out_read did not heed wait!!!", $time);
          $stop;
        end
    end


  //clock_0_out_write check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          clock_0_out_write_last_time <= 0;
      else if (1)
          clock_0_out_write_last_time <= clock_0_out_write;
    end


  //clock_0_out_write matches last port_name, which is an e_process
  always @(active_and_waiting_last_time or clock_0_out_write or clock_0_out_write_last_time)
    begin
      if (active_and_waiting_last_time & (clock_0_out_write != clock_0_out_write_last_time))
        begin
          $write("%0d ns: clock_0_out_write did not heed wait!!!", $time);
          $stop;
        end
    end


  //clock_0_out_writedata check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          clock_0_out_writedata_last_time <= 0;
      else if (1)
          clock_0_out_writedata_last_time <= clock_0_out_writedata;
    end


  //clock_0_out_writedata matches last port_name, which is an e_process
  always @(active_and_waiting_last_time or clock_0_out_write or clock_0_out_writedata or clock_0_out_writedata_last_time)
    begin
      if (active_and_waiting_last_time & (clock_0_out_writedata != clock_0_out_writedata_last_time) & clock_0_out_write)
        begin
          $write("%0d ns: clock_0_out_writedata did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu1_jtag_debug_module_arbitrator (
                                           // inputs:
                                            clk,
                                            cpu1_data_master_address_to_slave,
                                            cpu1_data_master_byteenable,
                                            cpu1_data_master_debugaccess,
                                            cpu1_data_master_read,
                                            cpu1_data_master_write,
                                            cpu1_data_master_writedata,
                                            cpu1_instruction_master_address_to_slave,
                                            cpu1_instruction_master_latency_counter,
                                            cpu1_instruction_master_read,
                                            cpu1_instruction_master_read_data_valid_ddr_sdram_s1_shift_register,
                                            cpu1_jtag_debug_module_readdata,
                                            cpu1_jtag_debug_module_resetrequest,
                                            reset_n,

                                           // outputs:
                                            cpu1_data_master_granted_cpu1_jtag_debug_module,
                                            cpu1_data_master_qualified_request_cpu1_jtag_debug_module,
                                            cpu1_data_master_read_data_valid_cpu1_jtag_debug_module,
                                            cpu1_data_master_requests_cpu1_jtag_debug_module,
                                            cpu1_instruction_master_granted_cpu1_jtag_debug_module,
                                            cpu1_instruction_master_qualified_request_cpu1_jtag_debug_module,
                                            cpu1_instruction_master_read_data_valid_cpu1_jtag_debug_module,
                                            cpu1_instruction_master_requests_cpu1_jtag_debug_module,
                                            cpu1_jtag_debug_module_address,
                                            cpu1_jtag_debug_module_begintransfer,
                                            cpu1_jtag_debug_module_byteenable,
                                            cpu1_jtag_debug_module_chipselect,
                                            cpu1_jtag_debug_module_debugaccess,
                                            cpu1_jtag_debug_module_readdata_from_sa,
                                            cpu1_jtag_debug_module_reset,
                                            cpu1_jtag_debug_module_reset_n,
                                            cpu1_jtag_debug_module_resetrequest_from_sa,
                                            cpu1_jtag_debug_module_write,
                                            cpu1_jtag_debug_module_writedata,