ddr_pll_cycloneii.v

来自「altera的fpga设计」· Verilog 代码 · 共 33 行

// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll


// ============================================================
// ============================================================
// CNX file retrieval info
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "85.0"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
//  Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
//  Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
//  Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "85.0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
//  Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
//  Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "85.0"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-90.0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
//  Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
//  Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "85.0"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"