📄 sysend.c
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PCI_RESOURCES * pRsrc; /* dec resource */
UINT32 pciBus; /* PCI Bus number */
UINT32 pciDevice; /* PCI Device number */
UINT32 pciFunc; /* PCI Function number */
unsigned int ix; /* counter */
int iy; /* counter */
int unit = 0; /* unit numbers */
UINT32 boardType = NONE; /* board type detected */
#endif
#ifdef INCLUDE_FEI82557END
FEI_RESOURCE * pFeiRes; /* FEI specific info */
#endif
#ifdef INCLUDE_DEC21X40END
/*
* Set the loops to be less per nano-second since this board is slower,
* than say, EBSA-285.
*/
dec21x40Loops = 1;
#endif
/*
* The following code tries to automatically detect and configure
* all instances of supported Ethernet cards.
*/
#ifdef INCLUDE_DEC21X40END |INCLUDE_FEI82557END
for (ix = 0; ix < BOARD_TYPE_NB; ix++)
{
for (iy = 0; iy < INTEGRATOR_MAX_END_DEVS; iy++)
{
if (pciFindDevice ((int) boardResources[ix].vendorId,
(int) boardResources[ix].deviceId,
iy, (int *)&pciBus, (int *)(&pciDevice),
(int *)(&pciFunc)) != OK)
{
break; /* skip to next vendor/product pair */
}
/* board detected */
boardType = boardResources[ix].type;
/*
* Update the END device table
*
* pciDevice for PCI cards plugged in is in the range 10 to 12.
*/
pRsrc = &(pciResources[pciDevice - 10]);
if (pRsrc->configType == AUTO)
{
/* Assign resources (interrupt, I/O) */
pciAssignResources (pciBus, pciDevice, pciFunc);
/* get memory base address and I/O base address */
#ifdef INCLUDE_DEC21X40END
if ((boardType >= DEC_START) &&
(boardType < (DEC_START + TYPE_ALLOC)))
{
pciConfigInLong ((int)pciBus, (int)pciDevice, (int)pciFunc,
PCI_CFG_BASE_ADDRESS_0,
(int *)&pRsrc->iobaseCsr);
pciConfigInLong ((int)pciBus, (int)pciDevice, (int)pciFunc,
PCI_CFG_BASE_ADDRESS_1,
(int *)&pRsrc->membaseCsr);
pciConfigInByte ((int)pciBus, (int)pciDevice, (int)pciFunc,
PCI_CFG_DEV_INT_LINE, (char *)&pRsrc->irq);
pRsrc->membaseCsr &= ~CSR_BASE_MSK;
pRsrc->iobaseCsr &= ~CSR_BASE_MSK;
/* overwrite the resource table with read value */
pRsrc->irqvec = IVEC_TO_INUM(pRsrc->irq);
}
#endif /* INCLUDE_DEC21X40END */
#ifdef INCLUDE_FEI82557END
if ((boardType >= FEI_START) &&
(boardType < (FEI_START + TYPE_ALLOC)))
{
pFeiRes = &feiResources [unit];
pciConfigInLong ((int)pciBus, (int)pciDevice, (int)pciFunc,
PCI_CFG_BASE_ADDRESS_0,
(int *)&pFeiRes->membaseCsr);
/* Convert to CPU address */
pFeiRes->membaseCsr += PCI2CPU_MEM_OFFSET;
pciConfigInLong ((int)pciBus, (int)pciDevice, (int)pciFunc,
PCI_CFG_BASE_ADDRESS_1,
(int *)&pFeiRes->iobaseCsr);
pFeiRes->iobaseCsr &= ~PCI_BASE_IO;
pFeiRes->iobaseCsr += PCI2CPU_IO_OFFSET;
pciConfigInByte (pciBus, pciDevice, pciFunc,
PCI_CFG_DEV_INT_LINE,
&pFeiRes->irq);
}
#endif /* INCLUDE_FEI82557END */
}
else /* Force PCI configuration */
{
#ifdef INCLUDE_DEC21X40END
if ((boardType >= DEC_START) &&
(boardType < (DEC_START + TYPE_ALLOC)))
{
/* set memory base address and I/O base address */
pciConfigOutLong (pciBus, pciDevice, pciFunc,
PCI_CFG_BASE_ADDRESS_0,
pRsrc->iobaseCsr | PCI_BASE_IO);
pciConfigOutLong (pciBus, pciDevice, pciFunc,
PCI_CFG_BASE_ADDRESS_1,
pRsrc->membaseCsr);
pciConfigOutByte (pciBus, pciDevice, pciFunc,
PCI_CFG_DEV_INT_LINE, pRsrc->irq);
}
#endif /* INCLUDE_DEC21X40END */
#ifdef INCLUDE_FEI82557END
if ((boardType >= FEI_START) &&
(boardType < (FEI_START + TYPE_ALLOC)))
{
pFeiRes = &feiResources [unit];
pciConfigOutLong (pciBus, pciDevice, pciFunc,
PCI_CFG_BASE_ADDRESS_0,
pRsrc->membaseCsr);
pFeiRes->membaseCsr = pRsrc->membaseCsr + PCI2CPU_MEM_OFFSET;
pciConfigOutLong (pciBus, pciDevice, pciFunc,
PCI_CFG_BASE_ADDRESS_1,
pRsrc->iobaseCsr | PCI_BASE_IO);
pFeiRes->iobaseCsr = pRsrc->iobaseCsr + PCI2CPU_IO_OFFSET;
pciConfigOutByte (pciBus, pciDevice, pciFunc,
PCI_CFG_DEV_INT_LINE, pRsrc->irq);
pFeiRes->irq = pRsrc->irq;
}
#endif /* INCLUDE_FEI82557END */
}
/*
* Update the END device table & dynamically create the load
* string we need for this device
*/
#ifdef INCLUDE_DEC21X40END
if ((boardType >= DEC_START) &&
(boardType < (DEC_START + TYPE_ALLOC)))
{
/*
* END load string format:
* "<deviceAddr>:<pciAddr>:<iVec>:<iLevel>:<numRds>:<numTds>:\
* <memBase>:<memSize>:<userFlags>:<phyAddr>:<pPhyTbl>:\
* <phyFlags>:<offset>"
*/
#ifdef INTEGRATOR_ENET_FIXED_BUF_ADRS
pRsrc->buf = (void *)sysEnetBufAdrs [unit];
pRsrc->cpuToPciOffset = 0;
#else /* INTEGRATOR_ENET_FIXED_BUF_ADRS */
pRsrc->cpuToPciOffset = PCI2DRAM_BASE_ADRS;
#ifdef INTEGRATOR_ENET_CHECK_BUFFERS
if (pRsrc->buf = cacheDmaMalloc (INTEGRATOR_DEC_BUF_SIZE),
pRsrc->buf == NULL)
{
/* cannot log msg at this point in initialisation timeline*/
return ERROR;
}
if (((UINT32)pRsrc->buf) < INTEGRATOR_HDR_SSRAM_SIZE)
{
/* cannot log msg at this point in initialisation timeline*/
return ERROR;
}
#else /* INTEGRATOR_ENET_CHECK_BUFFERS */
pRsrc->buf = (void *)NONE;
#endif /* INTEGRATOR_ENET_CHECK_BUFFERS */
#endif /* INTEGRATOR_ENET_FIXED_BUF_ADRS */
sprintf (endLoadStr[currentEndDevice],
"%#x:%#x:%#x:%#x:-1:-1:%#x:%#x:%#x:%#x:%#x:%#x:2:-1:0:",
/* Note: unit is prepended by the mux driver */
pRsrc->iobaseCsr + PCI2CPU_IO_OFFSET, /*devAdrs*/
pRsrc->cpuToPciOffset, /*pciMemBase*/
pRsrc->irq, pRsrc->irqvec, /*ivec,ilevel*/
/* numRds=default, numTds=default */
(UINT32)pRsrc->buf, /*memBase*/
INTEGRATOR_DEC_BUF_SIZE, /*memSize*/
boardResources[ix].decUsrFlags, /*usrFlags*/
1, 0, /* phyAddr,pMiiPhyTbl,*/
DEC_USR_MII_10MB |
DEC_USR_MII_HD | DEC_USR_MII_100MB |
DEC_USR_MII_FD | DEC_USR_MII_BUS_MON
);
endDevTbl[currentEndDevice].unit = unit++;
endDevTbl[currentEndDevice].endLoadFunc = dec21x40EndLoad;
endDevTbl[currentEndDevice].endLoadString =
endLoadStr[currentEndDevice];
endDevTbl[currentEndDevice].endLoan = DEC_BUFF_LOAN;
currentEndDevice++;
/* enable mapped memory and I/O addresses */
pciConfigOutWord (pciBus, pciDevice, pciFunc, PCI_CFG_COMMAND,
PCI_CMD_IO_ENABLE | PCI_CMD_MASTER_ENABLE);
/* disable sleep mode */
pciConfigOutByte (pciBus, pciDevice, pciFunc, PCI_CFG_MODE,
SLEEP_MODE_DIS);
}
#endif /* INCLUDE_DEC21X40END */
#ifdef INCLUDE_FEI82557END
if ((boardType >= FEI_START) &&
(boardType < (FEI_START + TYPE_ALLOC)))
{
#ifdef INTEGRATOR_ENET_FIXED_BUF_ADRS
pRsrc->buf = (void *)sysEnetBufAdrs [unit];
#else /* INTEGRATOR_ENET_FIXED_BUF_ADRS */
#ifdef INTEGRATOR_ENET_CHECK_BUFFERS
if (pRsrc->buf = cacheDmaMalloc (INTEGRATOR_FEI_BUF_SIZE),
pRsrc->buf == NULL)
{
/* cannot log msg at this point in initialisation timeline*/
return ERROR;
}
if (((UINT32)pRsrc->buf) < INTEGRATOR_HDR_SSRAM_SIZE)
{
/* cannot log msg at this point in initialisation timeline*/
return ERROR;
}
#else /* INTEGRATOR_ENET_CHECK_BUFFERS */
pRsrc->buf = (void *)NONE;
#endif /* INTEGRATOR_ENET_CHECK_BUFFERS */
#endif /* INTEGRATOR_ENET_FIXED_BUF_ADRS */
sprintf (endLoadStr[currentEndDevice],
"0x%08X:0x%08X:0x%X:0x%X:0x00:2",
(UINT32)pRsrc->buf, INTEGRATOR_FEI_BUF_SIZE,
INTEGRATOR_FEI_NUM_CFDS, INTEGRATOR_FEI_NUM_RFDS);
endDevTbl[currentEndDevice].unit = unit++;
endDevTbl[currentEndDevice].endLoadFunc = fei82557EndLoad;
endDevTbl[currentEndDevice].endLoadString =
endLoadStr[currentEndDevice];
endDevTbl[currentEndDevice].endLoan = 1;
currentEndDevice++;
/* enable mapped I/O addresses */
pciConfigOutWord (pciBus, pciDevice, pciFunc,
PCI_CFG_COMMAND, PCI_CMD_IO_ENABLE |
PCI_CMD_MASTER_ENABLE);
}
#endif /* INCLUDE_FEI82557END */
/* Configured the maximum number of adaptors? */
if (currentEndDevice == INTEGRATOR_MAX_END_DEVS)
{
return OK;
}
}
}
if ((unit == 0) || (pciDevice > PCI_MAX_DEV))
{
return ERROR;
}
#endif
return OK;
}
#ifdef INCLUDE_DEC21X40END
/*******************************************************************************
*
* sysLanIntEnable - enable dec21X4X interrupts
*
* This routine enables dec21X4X interrupts. This may involve operations on
* interrupt control hardware.
*
* RETURNS: OK or ERROR for invalid arguments.
*/
STATUS sysLanIntEnable
(
int level /* level number */
)
{
return (intEnable(level));
}
/*******************************************************************************
*
* sysLanIntDisable - disable dec21X4X interrupts
*
* This routine disables dec21X4X interrupts. This may involve operations on
* interrupt control hardware.
*
* RETURNS: OK or ERROR for invalid arguments.
*/
STATUS sysLanIntDisable
(
int level /* level number */
)
{
return (intDisable(level));
}
/*******************************************************************************
*
* sysDec21x40EnetAddrGet - get Ethernet address
*
* This routine provides a target-specific interface for accessing a
* device Ethernet address.
*
* RETURNS: OK or ERROR if could not be obtained.
*/
STATUS sysDec21x40EnetAddrGet
(
int unit,
char * enetAdrs
)
{
/*
* There isn't a target-specific interface for accessing a
* device Ethernet address.
*/
return (ERROR);
}
#endif /* INCLUDE_DEC21X40END */
#ifdef INCLUDE_FEI82557END
#ifndef INTEGRATOR_ENET_FIXED_BUF_ADRS
/*******************************************************************************
*
* sys557CpuToPci - Convert a CPU memory address to a PCI address
*
* Must convert virtual address to a physical address, then convert the
* physical address to a PCI address (PCI2DRAM_BASE_ADRS is the offset of the
* CPU's memory on the PCI bus,
* i.e. PCI address = (CPU physical address + PCI2DRAM_BASE_ADRS)
*
* This routine works only for addresses in SDRAM.
*
* WARNING: No attempt is made to ensure that the address passed into this
* function is valid.
*
* RETURNS: PCI address corresponding to the CPU virtual address provided
*/
UINT32 sys557CpuToPci
(
int unit, /* ignored */
UINT32 addr
)
{
unit = unit; /* silence compiler */
#ifdef SYS_FEI_DEBUG
logMsg ("sys557CpuToPci %#x -> %#x\n", addr, addr + PCI2DRAM_BASE_ADRS,
0,0,0,0);
#endif
return (UINT32)((CACHE_DMA_VIRT_TO_PHYS(addr)) + PCI2DRAM_BASE_ADRS);
}
/*******************************************************************************
*
* sys557PciToCpu - Convert a PCI memory address to a CPU address
*
* This is the reverse of the previous function. Here we convert from a PCI
* address to a physical address in the CPU's address space, then use the
* current translation tables to find the corresponding virtual address.
*
* This routine works only for addresses in SDRAM.
*
* WARNING: No attempt is made to ensure that the address passed into this
* function is valid.
*
* RETURNS: CPU virtual address for specified PCI address
*/
UINT32 sys557PciToCpu
(
int unit, /* ignored */
UINT32 addr
)
{
unit = unit; /* silence compiler */
#ifdef SYS_FEI_DEBUG
logMsg ("sys557PciToCpu %#x -> %#x\n", addr, addr - PCI2DRAM_BASE_ADRS,
0,0,0,0);
#endif
return (UINT32)(CACHE_DMA_PHYS_TO_VIRT(addr - PCI2DRAM_BASE_ADRS));
}
#endif /* INTEGRATOR_ENET_FIXED_BUF_ADRS */
/*******************************************************************************
*
* sysDelay - a small delay
*
*/
void sysDelay (void)
{
volatile UINT32 p;
/* Read from ROM, a known timing */
p = *(volatile UINT32 *)ROM_TEXT_ADRS;
/*
* Create a little more delay: some arithmetic operations that
* involve immediate constants that cannot be performed in one
* instruction. Clearly it is possible that compiler changes will
* affect this code and leave this no longer calibrated.
*/
p &=0xffff;
p +=0xff11;
p +=0xff51;
return;
}
/*******************************************************************************
*
* sys557Init - prepare LAN adapter for 82557 initialization
*
* This routine is expected to perform any adapter-specific or target-specific
* initialization that must be done prior to initializing the 82557.
*
* The 82557 driver calls this routine from the driver attach routine before
* any other routines in this library.
*
* This routine returns the interrupt level the <pIntLvl> parameter.
*
* RETURNS: OK or ERROR if the adapter could not be prepared for initialization.
*/
STATUS sys557Init
(
int unit, /* unit number */
FEI_BOARD_INFO * pBoard /* board information for the end driver */
)
{
volatile FEI_RESOURCE * pReso = &feiResources [unit];
UINT16 sum = 0;
int ix;
int iy;
UINT16 value;
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