📄 at91emac-old.h
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#define AT91C_EMAC_TOVR ((unsigned int) 0x1 << 3) /* (EMAC) */
#define AT91C_EMAC_TUND ((unsigned int) 0x1 << 4) /* (EMAC) */
#define AT91C_EMAC_RTRY ((unsigned int) 0x1 << 5) /* (EMAC) */
#define AT91C_EMAC_TBRE ((unsigned int) 0x1 << 6) /* (EMAC) */
#define AT91C_EMAC_TCOM ((unsigned int) 0x1 << 7) /* (EMAC) */
#define AT91C_EMAC_TIDLE ((unsigned int) 0x1 << 8) /* (EMAC) */
#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) /* (EMAC) */
#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) /* (EMAC) */
#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) /* (EMAC) */
/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) /* (EMAC) */
#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) /* (EMAC) */
#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) /* (EMAC) */
#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) /* (EMAC) */
#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) /* (EMAC) */
#define AT91C_EMAC_HIGH ((unsigned int) 0x1 << 30) /* (EMAC) */
#define AT91C_EMAC_LOW ((unsigned int) 0x1 << 31) /* (EMAC)*/
/***************************************************************************** */
/* EMAC PIO DEFINITIONS FOR AT91RM9200 */
/***************************************************************************** */
#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) /* Pin Controlled by PA14*/
#define AT91C_PA14_ERXER ((unsigned int) AT91C_PIO_PA14) /* Ethernet MAC Receive Error*/
#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) /* Pin Controlled by PA12*/
#define AT91C_PA12_ERX0 ((unsigned int) AT91C_PIO_PA12) /* Ethernet MAC Receive Data 0*/
#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) /* Pin Controlled by PA13*/
#define AT91C_PA13_ERX1 ((unsigned int) AT91C_PIO_PA13) /* Ethernet MAC Receive Data 1*/
#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) /* Pin Controlled by PA8*/
#define AT91C_PA8_ETXEN ((unsigned int) AT91C_PIO_PA8) /* Ethernet MAC Transmit Enable*/
#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) /* Pin Controlled by PA16*/
#define AT91C_PA16_EMDIO ((unsigned int) AT91C_PIO_PA16) /* Ethernet MAC Management Data Input/Output*/
#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) /* Pin Controlled by PA9*/
#define AT91C_PA9_ETX0 ((unsigned int) AT91C_PIO_PA9) /* Ethernet MAC Transmit Data 0*/
#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) /* Pin Controlled by PA10*/
#define AT91C_PA10_ETX1 ((unsigned int) AT91C_PIO_PA10) /* Ethernet MAC Transmit Data 1*/
#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) /* Pin Controlled by PA11*/
#define AT91C_PA11_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PA11) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid*/
#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) /* Pin Controlled by PA15*/
#define AT91C_PA15_EMDC ((unsigned int) AT91C_PIO_PA15) /* Ethernet MAC Management Data Clock*/
#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7*/
#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock*/
/* ***************************************************************************** */
/* SOFTWARE API DEFINITION FOR Power Management Controler */
/* ***************************************************************************** */
typedef struct _AT91S_PMC {
AT91_REG PMC_SCER; /* System Clock Enable Register */
AT91_REG PMC_SCDR; /* System Clock Disable Register*/
AT91_REG PMC_SCSR; /* System Clock Status Register*/
AT91_REG Reserved0[1]; /* */
AT91_REG PMC_PCER; /* Peripheral Clock Enable Register*/
AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register*/
AT91_REG PMC_PCSR; /* Peripheral Clock Status Register*/
AT91_REG Reserved1[5]; /* */
AT91_REG PMC_MCKR; /* Master Clock Register*/
AT91_REG Reserved2[3]; /* */
AT91_REG PMC_PCKR[8]; /* Programmable Clock Register*/
AT91_REG PMC_IER; /* Interrupt Enable Register*/
AT91_REG PMC_IDR; /* Interrupt Disable Register*/
AT91_REG PMC_SR; /* Status Register*/
AT91_REG PMC_IMR; /* Interrupt Mask Register*/
} AT91S_PMC, *AT91PS_PMC;
#define AT91C_ID_EMAC ((unsigned int) 24) /* Ethernet MAC*/
/* ========== Register definition for EMAC peripheral ========== */
#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFBC020) /* (EMAC) Receive Status Register*/
#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFBC034) /* (EMAC) PHY Maintenance Register*/
#define AT91C_EMAC_HSH ((AT91_REG *) 0xFFFBC090) /* (EMAC) Hash Address High[63:32]*/
#define AT91C_EMAC_MCOL ((AT91_REG *) 0xFFFBC048) /* (EMAC) Multiple Collision Frame Register*/
#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFBC028) /* (EMAC) Interrupt Enable Register*/
#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFBC0A4) /* (EMAC) Specific Address 2 High, Last 2 bytes*/
#define AT91C_EMAC_HSL ((AT91_REG *) 0xFFFBC094) /* (EMAC) Hash Address Low[31:0]*/
#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFBC05C) /* (EMAC) Late Collision Register*/
#define AT91C_EMAC_OK ((AT91_REG *) 0xFFFBC04C) /* (EMAC) Frames Received OK Register*/
#define AT91C_EMAC_CFG ((AT91_REG *) 0xFFFBC004) /* (EMAC) Network Configuration Register*/
#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFBC0A8) /* (EMAC) Specific Address 3 Low, First 4 bytes*/
#define AT91C_EMAC_SEQE ((AT91_REG *) 0xFFFBC050) /* (EMAC) Frame Check Sequence Error Register*/
#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFBC060) /* (EMAC) Excessive Collision Register*/
#define AT91C_EMAC_ELR ((AT91_REG *) 0xFFFBC070) /* (EMAC) Excessive Length Error Register*/
#define AT91C_EMAC_SR ((AT91_REG *) 0xFFFBC008) /* (EMAC) Network Status Register*/
#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFBC018) /* (EMAC) Receive Buffer Queue Pointer*/
#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFBC064) /* (EMAC) Carrier Sense Error Register*/
#define AT91C_EMAC_RJB ((AT91_REG *) 0xFFFBC074) /* (EMAC) Receive Jabber Register*/
#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFBC078) /* (EMAC) Undersize Frame Register*/
#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFBC02C) /* (EMAC) Interrupt Disable Register*/
#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFBC098) /* (EMAC) Specific Address 1 Low, First 4 bytes*/
#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFBC030) /* (EMAC) Interrupt Mask Register*/
#define AT91C_EMAC_FRA ((AT91_REG *) 0xFFFBC040) /* (EMAC) Frames Transmitted OK Register*/
#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFBC0AC) /* (EMAC) Specific Address 3 High, Last 2 bytes*/
#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFBC09C) /* (EMAC) Specific Address 1 High, Last 2 bytes*/
#define AT91C_EMAC_SCOL ((AT91_REG *) 0xFFFBC044) /* (EMAC) Single Collision Frame Register*/
#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFBC054) /* (EMAC) Alignment Error Register*/
#define AT91C_EMAC_TAR ((AT91_REG *) 0xFFFBC00C) /* (EMAC) Transmit Address Register*/
#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFBC0B0) /* (EMAC) Specific Address 4 Low, First 4 bytes*/
#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFBC0A0) /* (EMAC) Specific Address 2 Low, First 4 bytes*/
#define AT91C_EMAC_TUE ((AT91_REG *) 0xFFFBC068) /* (EMAC) Transmit Underrun Error Register*/
#define AT91C_EMAC_DTE ((AT91_REG *) 0xFFFBC058) /* (EMAC) Deferred Transmission Frame Register*/
#define AT91C_EMAC_TCR ((AT91_REG *) 0xFFFBC010) /* (EMAC) Transmit Control Register*/
#define AT91C_EMAC_CTL ((AT91_REG *) 0xFFFBC000) /* (EMAC) Network Control Register*/
#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFBC0B4) /* (EMAC) Specific Address 4 High, Last 2 bytesr*/
#define AT91C_EMAC_CDE ((AT91_REG *) 0xFFFBC06C) /* (EMAC) Code Error Register*/
#define AT91C_EMAC_SQEE ((AT91_REG *) 0xFFFBC07C) /* (EMAC) SQE Test Error Register*/
#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFBC014) /* (EMAC) Transmit Status Register*/
#define AT91C_EMAC_DRFC ((AT91_REG *) 0xFFFBC080) /* (EMAC) Discarded RX Frame Register*/
/* MII registers definition */
#define MII_STS_REG 0x01
#define MII_STS2_REG 0x11
/*****************************************************************************/
/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */
/*****************************************************************************/
#if 0
typedef struct _AT91S_PIO {
AT91_REG PIO_PER; /* PIO Enable Register */
AT91_REG PIO_PDR; /* PIO Disable Register*/
AT91_REG PIO_PSR; /* PIO Status Register*/
AT91_REG Reserved0[1]; /* */
AT91_REG PIO_OER; /* Output Enable Register*/
AT91_REG PIO_ODR; /* Output Disable Registerr*/
AT91_REG PIO_OSR; /* Output Status Register*/
AT91_REG Reserved1[1]; /* */
AT91_REG PIO_IFER; /* Input Filter Enable Register*/
AT91_REG PIO_IFDR; /* Input Filter Disable Register*/
AT91_REG PIO_IFSR; /* Input Filter Status Register*/
AT91_REG Reserved2[1]; /* */
AT91_REG PIO_SODR; /* Set Output Data Register*/
AT91_REG PIO_CODR; /* Clear Output Data Register*/
AT91_REG PIO_ODSR; /* Output Data Status Register*/
AT91_REG PIO_PDSR; /* Pin Data Status Register*/
AT91_REG PIO_IER; /* Interrupt Enable Register*/
AT91_REG PIO_IDR; /* Interrupt Disable Register*/
AT91_REG PIO_IMR; /* Interrupt Mask Register*/
AT91_REG PIO_ISR; /* Interrupt Status Register*/
AT91_REG PIO_MDER; /* Multi-driver Enable Register*/
AT91_REG PIO_MDDR; /* Multi-driver Disable Register*/
AT91_REG PIO_MDSR; /* Multi-driver Status Register*/
AT91_REG Reserved3[1]; /* */
AT91_REG PIO_PPUDR; /* Pull-up Disable Register*/
AT91_REG PIO_PPUER; /* Pull-up Enable Register*/
AT91_REG PIO_PPUSR; /* Pad Pull-up Status Register*/
AT91_REG Reserved4[1]; /* */
AT91_REG PIO_ASR; /* Select A Register*/
AT91_REG PIO_BSR; /* Select B Register*/
AT91_REG PIO_ABSR; /* AB Select Status Register*/
AT91_REG Reserved5[9]; /* */
AT91_REG PIO_OWER; /* Output Write Enable Register*/
AT91_REG PIO_OWDR; /* Output Write Disable Register*/
AT91_REG PIO_OWSR; /* Output Write Status Register*/
} AT91S_PIO, *AT91PS_PIO;
#endif
#endif /* AT91C_EMAC_H*/
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