at91emac-old.h

ATMEL920T的BSP及ETH等已经设备驱动程序

/*----------------------------------------------------------------------------	*/
/*         ATMEL Microcontroller Software Support  -  ROUSSET  -							*/
/*----------------------------------------------------------------------------	*/
/* The software is delivered "AS IS" without warranty or condition of any					*/	
/* kind, either express, implied or statutory. This includes without							*/
/* limitation any warranty or condition with respect to merchantability or						*/
/* fitness for any particular purpose, or against the infringements of						*/
/* intellectual property rights of others.												*/
/*----------------------------------------------------------------------------	*/
/* File Name           : Emac.h														*/
/* Object              : Emac header file													*/
/* Creation            : Hi   11/18/2002													*/		
/*																				*/
/*----------------------------------------------------------------------------	*/
#ifndef AT91C_EMAC_H
#define AT91C_EMAC_H

/* Allows to display all IP header in the main.c*/
/* If not defined, only ICMP packets are displayed*/
#define AT91C_DISPLAY_ALL_IPHEADER		1

#define NB_ETH_RX_PACKETS		100			/* Number of ethernet packets buffer*/
#define ETH_PACKET_SIZE 		2048        /* Size of an ethernet packet*/
#define AT91C_NO_IPPACKET		0
#define AT91C_IPPACKET	        1

#define ARP_REQUEST				0x0001
#define ARP_REPLY				0x0002
#define PROT_ARP				0x0806
#define PROT_IP					0x0800
#define PROT_ICMP				0x01
#define ICMP_ECHO_REQUEST		0x08
#define ICMP_ECHO_REPLY			0x00

#define SWAP16(x)	(((x & 0xff) << 8) | (x >> 8))

/* Transfer descriptor structure*/
typedef struct _AT91S_TdDescriptor {
	unsigned int addr;
	unsigned int size;
}AT91S_TdDescriptor, *AT91PS_TdDescriptor;


/* IP Header structure*/
typedef struct _AT91S_IPheader {
	unsigned char	ip_hl_v;	/* header length and version	*/
	unsigned char	ip_tos;		/* type of service		*/
	unsigned short	ip_len;		/* total length			*/
	unsigned short	ip_id;		/* identification		*/
	unsigned short	ip_off;		/* fragment offset field	*/
	unsigned char	ip_ttl;		/* time to live			*/
	unsigned char	ip_p;		/* protocol			*/
	unsigned short	ip_sum;		/* checksum			*/
	unsigned char	ip_src[4];		/* Source IP address		*/
	unsigned char	ip_dst[4];		/* Destination IP address	*/
} AT91S_IPheader, *AT91PS_IPheader;

/* ICMP echo header structure */
typedef struct _AT91S_IcmpEchoHdr {
    unsigned char   type;       /* type of message */
    unsigned char   code;       /* type subcode */
    unsigned short  cksum;      /* ones complement cksum of struct */
    unsigned short  id;         /* identifier */
    unsigned short  seq;        /* sequence number */
}AT91S_IcmpEchoHdr, *AT91PS_IcmpEchoHdr;

typedef volatile unsigned int AT91_REG;/* Hardware register definition	*/

typedef struct _AT91S_EMAC {
	AT91_REG	 EMAC_CTL; 		/* Network Control Register	*/
	AT91_REG	 EMAC_CFG; 		/* Network Configuration Register	*/
	AT91_REG	 EMAC_SR; 		/* Network Status Register	*/
	AT91_REG	 EMAC_TAR; 		/* Transmit Address Register	*/
	AT91_REG	 EMAC_TCR; 		/* Transmit Control Register	*/
	AT91_REG	 EMAC_TSR; 		/* Transmit Status Register */
	AT91_REG	 EMAC_RBQP; 	/* Receive Buffer Queue Pointer*/
	AT91_REG	 Reserved0[1]; 	/* */
	AT91_REG	 EMAC_RSR; 		/* Receive Status Register*/
	AT91_REG	 EMAC_ISR; 		/* Interrupt Status Register*/
	AT91_REG	 EMAC_IER; 		/* Interrupt Enable Register*/
	AT91_REG	 EMAC_IDR; 		/* Interrupt Disable Register*/
	AT91_REG	 EMAC_IMR; 		/* Interrupt Mask Register*/
	AT91_REG	 EMAC_MAN; 	/* PHY Maintenance Register*/
	AT91_REG	 Reserved1[2]; 	 /* */
	AT91_REG	 EMAC_FRA; 		/* Frames Transmitted OK Register*/
	AT91_REG	 EMAC_SCOL; 	/* Single Collision Frame Register*/
	AT91_REG	 EMAC_MCOL; 	/* Multiple Collision Frame Register*/
	AT91_REG	 EMAC_OK; 		/* Frames Received OK Register*/
	AT91_REG	 EMAC_SEQE; 	/* Frame Check Sequence Error Register*/
	AT91_REG	 EMAC_ALE; 		/* Alignment Error Register*/
	AT91_REG	 EMAC_DTE; 		/* Deferred Transmission Frame Register*/
	AT91_REG	 EMAC_LCOL; 	/* Late Collision Register*/
	AT91_REG	 EMAC_ECOL; 	/* Excessive Collision Register*/
	AT91_REG	 EMAC_CSE; 		/* Carrier Sense Error Register*/
	AT91_REG	 EMAC_TUE; 		/* Transmit Underrun Error Register*/
	AT91_REG	 EMAC_CDE; 		/* Code Error Register*/
	AT91_REG	 EMAC_ELR; 		/* Excessive Length Error Register*/
	AT91_REG	 EMAC_RJB; 		/* Receive Jabber Register*/
	AT91_REG	 EMAC_USF; 		/* Undersize Frame Register*/
	AT91_REG	 EMAC_SQEE; 	/* SQE Test Error Register*/
	AT91_REG	 EMAC_DRFC; 	/* Discarded RX Frame Register*/
	AT91_REG	 Reserved2[3]; 	/* */
	AT91_REG	 EMAC_HSH; 		/* Hash Address High[63:32]*/
	AT91_REG	 EMAC_HSL; 		/* Hash Address Low[31:0]*/
	AT91_REG	 EMAC_SA1L; 	/* Specific Address 1 Low, First 4 bytes*/
	AT91_REG	 EMAC_SA1H; 	/* Specific Address 1 High, Last 2 bytes*/
	AT91_REG	 EMAC_SA2L; 	/* Specific Address 2 Low, First 4 bytes*/
	AT91_REG	 EMAC_SA2H; 	/* Specific Address 2 High, Last 2 bytes*/
	AT91_REG	 EMAC_SA3L; 	/* Specific Address 3 Low, First 4 bytes*/
	AT91_REG	 EMAC_SA3H; 	/* Specific Address 3 High, Last 2 bytes*/
	AT91_REG	 EMAC_SA4L; 	/* Specific Address 4 Low, First 4 bytes*/
	AT91_REG	 EMAC_SA4H; 	/* Specific Address 4 High, Last 2 bytesr*/
} AT91S_EMAC, *AT91PS_EMAC;

/* -------- EMAC_CTL : (EMAC Offset: 0x0)  -------- */
#define AT91C_EMAC_LB         ((unsigned int) 0x1 <<  0) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level.*/
#define AT91C_EMAC_LBL        ((unsigned int) 0x1 <<  1) /* (EMAC) Loopback local. */
#define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) /* (EMAC) Receive enable. */
#define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) /* (EMAC) Transmit enable. */
#define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) /* (EMAC) Management port enable. */
#define AT91C_EMAC_CSR        ((unsigned int) 0x1 <<  5) /* (EMAC) Clear statistics registers. */
#define AT91C_EMAC_ISR        ((unsigned int) 0x1 <<  6) /* (EMAC) Increment statistics registers. */
#define AT91C_EMAC_WES        ((unsigned int) 0x1 <<  7) /* (EMAC) Write enable for statistics registers. */
#define AT91C_EMAC_BP         ((unsigned int) 0x1 <<  8) /* (EMAC) Back pressure. */
/* -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- */
#define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) /* (EMAC) Speed. */
#define AT91C_EMAC_FD         ((unsigned int) 0x1 <<  1) /* (EMAC) Full duplex. */
#define AT91C_EMAC_BR         ((unsigned int) 0x1 <<  2) /* (EMAC) Bit rate. */
#define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) /* (EMAC) Copy all frames. */
#define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) /* (EMAC) No broadcast. */
#define AT91C_EMAC_MTI        ((unsigned int) 0x1 <<  6) /* (EMAC) Multicast hash enable*/
#define AT91C_EMAC_UNI        ((unsigned int) 0x1 <<  7) /* (EMAC) Unicast hash enable. */
#define AT91C_EMAC_BIG        ((unsigned int) 0x1 <<  8) /* (EMAC) Receive 1522 bytes. */
#define AT91C_EMAC_EAE        ((unsigned int) 0x1 <<  9) /* (EMAC) External address match enable. */
#define AT91C_EMAC_CLK        ((unsigned int) 0x3 << 10) /* (EMAC) */
#define 	AT91C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) /* (EMAC) HCLK divided by 8*/
#define 	AT91C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) /* (EMAC) HCLK divided by 16*/
#define 	AT91C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) /* (EMAC) HCLK divided by 32*/
#define 	AT91C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) /* (EMAC) HCLK divided by 64*/
#define AT91C_EMAC_RTY        ((unsigned int) 0x1 << 12) /* (EMAC) */
#define AT91C_EMAC_RMII       ((unsigned int) 0x1 << 13) /* (EMAC) */
/* -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- */
#define AT91C_EMAC_MDIO       ((unsigned int) 0x1 <<  1) /* (EMAC) */
#define AT91C_EMAC_IDLE       ((unsigned int) 0x1 <<  2) /* (EMAC) */
/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- */
#define AT91C_EMAC_LEN        ((unsigned int) 0x7FF <<  0) /* (EMAC) */
#define AT91C_EMAC_NCRC       ((unsigned int) 0x1 << 15) /* (EMAC) */
/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- */
#define AT91C_EMAC_OVR        ((unsigned int) 0x1 <<  0) /* (EMAC) */
#define AT91C_EMAC_COL        ((unsigned int) 0x1 <<  1) /* (EMAC) */
#define AT91C_EMAC_RLE        ((unsigned int) 0x1 <<  2) /* (EMAC) */
#define AT91C_EMAC_TXIDLE     ((unsigned int) 0x1 <<  3) /* (EMAC) */
#define AT91C_EMAC_BNQ        ((unsigned int) 0x1 <<  4) /* (EMAC) */
#define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) /* (EMAC) */
#define AT91C_EMAC_UND        ((unsigned int) 0x1 <<  6) /* (EMAC) */
/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
#define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) /* (EMAC) */
#define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) /* (EMAC) */
/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
#define AT91C_EMAC_DONE       ((unsigned int) 0x1 <<  0) /* (EMAC) */
#define AT91C_EMAC_RCOM       ((unsigned int) 0x1 <<  1) /* (EMAC) */
#define AT91C_EMAC_RBNA       ((unsigned int) 0x1 <<  2) /* (EMAC) */