📄 syslib.c
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* Interrupts not in this list will be serviced least-significant bit
* first at a lower priority than those in the list.
*
* To use lowest-bit = highest-priority, reverse the sense of the
* condition below so that ambaIntLvlPriMap is a zero pointer.
*/
#if TRUE
LOCAL int ambaIntLvlPriMap[AMBA_INT_NUM_LEVELS] =
{
INT_SRC_FIQ, /* FIQ interrupt */
INT_SRC_SYSIRQ, /* SYS interrupt */
INT_SRC_EMAC, /* EMAC interrupt */
INT_SRC_IRQ0, /* IRQ0 interrupt */
-1 /* list terminator */
};
#else
LOCAL int *ambaIntLvlPriMap = 0;
#endif
#else
/*
* This array maps interrupt levels to mask patterns. The interrupt level
* is the index, the data is the mask value. A mask bit enables one
* level. The mask value is 'and'd with the ambaIntLvlEnabled value
* before writing to the chip.
*/
#if 0
LOCAL UINT32 ambaIntLvlMask[AMBA_INT_NUM_LEVELS + 1] = /* int level mask */
{
0x00000000, /* level 0, all disabled */
0x00000001, 0x00000003, 0x00000007, 0x0000000f,
0x0000001f, 0x0000003f, 0x0000007f, 0x000000ff,
0x000001ff, 0x000003ff, 0x000007ff, 0x00000fff,
0x00001fff, 0x00003fff, 0x00007fff, 0x0000ffff,
0x0001ffff, 0x0003ffff, 0x0007ffff, 0x000fffff,
0x001fffff, 0x003fffff /* level 22, all enabled */
};
#endif
LOCAL UINT32 ambaIntLvlMask[AMBA_INT_NUM_LEVELS + 1] = /* int level mask */
{
0x00000000, /* level 0, all disabled */
0x00000001, /* FIQ enabled */
0x00000003, /* SYS enabled */
0x01000003, /* EMAC enabled */
0xff000003, /* IRQ0-IRQ6 enabled */
0xff00003f, /* PIOA-PIOD enabled */
0xff7e003f,
0xff7ff43f,
0xffffffff /* level 8 all enabled */
};
/*#if AMBA_INT_NUM_LEVELS != 22*/
#if AMBA_INT_NUM_LEVELS != 8
# error ambaIntLvlMask is wrong size for number of levels
#endif
#endif /* ifdef AMBA_INT_PRIORITY_MAP */
/* defines */
/* externals */
IMPORT int at91IntDevInit (void);
IMPORT void sysIntStackSplit (char *, long);
/* globals */
/* forward LOCAL functions declarations */
/* forward declarations */
char * sysPhysMemTop (void);
#if defined (INCLUDE_USB)
void sysUsbPciInit(void);
#endif
/* included source files */
#ifdef INCLUDE_FLASH
/*#include "mem/nvRamToFlash.c"*/
#include "flashMem.c"
#include "../../driver/flash/at49bv322a.c"
#include "../../driver/flash/nvram49.c"
#else
#include "mem/nullNvRam.c"
#endif
#include "vme/nullVme.c"
#include "sysSerial.c"
/*#include "timer/ambaTimer.c"*/
#include "../../driver/timer/ambaTimer.c"
#include "primeCellSio.c"
/*#include "intrCtl/ambaIntrCtl.c"*/
#include "../../driver/intrctl/at91IntrCtl.c"
#include "../../driver/intrctl/reset.c"
#include "../../driver/uart/sc16c554.c"
#include "../../driver/uart/modem.c"
#include "../../driver/led/led.c"
#ifdef INCLUDE_END
#include "sysEnd.c"
#endif
#ifdef INCLUDE_WINDML
#include "ambaKbd.c"
#include "ambaMse.c"
#include "sysWindML.c"
#endif /* INCLUDE_WINDML */
void sysIRQInt(void);
/*******************************************************************************
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.
*
* NOTE
* This routine does not include all of the possible variants, and the
* inclusion of a variant in here does not mean that it is supported.
*
* RETURNS: A pointer to a string identifying the board and CPU.
*/
char *sysModel (void)
{
#if defined(CPU_7TDMI)
return "ARM Integrator - ARM7TDMI (ARM)";
#elif defined(CPU_7TDMI_T)
return "ARM Integrator - ARM7TDMI (Thumb)";
#elif defined(CPU_720T)
return "ARM Integrator - ARM720T (ARM)";
#elif defined(CPU_720T_T)
return "ARM Integrator - ARM720T (Thumb)";
#elif defined(CPU_740T)
return "ARM Integrator - ARM740T (ARM)";
#elif defined(CPU_740T_T)
return "ARM Integrator - ARM740T (Thumb)";
#elif defined(CPU_920T)
return "ARM Integrator - ARM920T (ARM)";
#elif defined(CPU_920T_T)
return "ARM Integrator - ARM920T (Thumb)";
#elif defined(CPU_940T)
return "ARM Integrator - ARM940T (ARM)";
#elif defined(CPU_940T_T)
return "ARM Integrator - ARM940T (Thumb)";
#elif defined(CPU_946ES)
return "ARM Integrator - ARM946ES (ARM)";
#elif defined(CPU_946ES_T)
return "ARM Integrator - ARM946ES (Thumb)";
#elif defined(CPU_966ES)
return "ARM Integrator - ARM966ES (ARM)";
#elif defined(CPU_966ES_T)
return "ARM Integrator - ARM966ES (Thumb)";
#else
#error CPU not supported
#endif /* defined(CPU_7TDMI) */
}
/*******************************************************************************
*
* sysBspRev - return the BSP version with the revision eg 1.2/<x>
*
* This function returns a pointer to a BSP version with the revision.
* e.g. 1.2/<x>. BSP_REV is concatenated to BSP_VERSION to form the
* BSP identification string.
*
* RETURNS: A pointer to the BSP version/revision string.
*/
char * sysBspRev (void)
{
return (BSP_VERSION BSP_REV);
}
#if defined(CPU_720T) || defined(CPU_720T_T) || \
defined(CPU_740T) || defined(CPU_740T_T) || \
defined(CPU_920T) || defined(CPU_920T_T) || \
defined(CPU_940T) || defined(CPU_940T_T) || \
defined(CPU_946ES) || defined(CPU_946ES_T)
/*******************************************************************************
*
* sysHwInit0 - perform early BSP-specific initialisation
*
* This routine performs such BSP-specific initialisation as is necessary before
* the architecture-independent cacheLibInit can be called. It is called
* from usrInit() before cacheLibInit(), before sysHwInit() and before BSS
* has been cleared.
*
* RETURNS: N/A
*/
void sysHwInit0 (void)
{
#ifdef INCLUDE_CACHE_SUPPORT
/*
* Install the appropriate cache library, no address translation
* routines are required for this BSP, as the default memory map has
* virtual and physical addresses the same.
*/
#if defined(CPU_720T) || defined(CPU_720T_T)
cacheArm720tLibInstall (NULL, NULL);
#elif defined(CPU_740T) || defined(CPU_740T_T)
cacheArm740tLibInstall (NULL, NULL);
#elif defined(CPU_920T) || defined(CPU_920T_T)
cacheArm920tLibInstall (NULL, NULL);
#elif defined(CPU_940T) || defined(CPU_940T_T)
cacheArm940tLibInstall (NULL, NULL);
#elif defined(CPU_946ES) || defined(CPU_946ES_T)
cacheArm946eLibInstall (NULL, NULL);
#endif
#endif /* INCLUDE_CACHE_SUPPORT */
#if defined(INCLUDE_MMU)
/* Install the appropriate MMU library and translation routines */
#if defined(CPU_720T) || defined(CPU_720T_T)
mmuArm720tLibInstall (NULL, NULL);
#elif defined(CPU_740T) || defined(CPU_740T_T)
mmuArm740tLibInstall (NULL, NULL);
#elif defined(CPU_920T) || defined(CPU_920T_T)
mmuArm920tLibInstall (NULL, NULL);
#elif defined(CPU_940T) || defined(CPU_940T_T)
mmuArm940tLibInstall (NULL, NULL);
#elif defined(CPU_946ES) || defined(CPU_946ES_T)
mmuArm946eLibInstall (NULL, NULL);
#endif
#endif /* defined(INCLUDE_MMU) */
return;
}
#endif /* defined(720T/740T/920T/940T/946ES) */
#if defined(INCLUDE_PCI)
/*******************************************************************************
*
* sysV3Init - initialise the V3 PCI bridge controller
*
* This function initialises the V3 chip which controls the PCI bridge.
*
* RETURNS: N/A
*/
void sysV3Init (void)
{
volatile int i, j;
/* setting this register will take the V3 out of reset */
*(UINT32 *)(INTEGRATOR_SC_PCIENABLE) = 1;
/* wait a few usecs to settle the device and the PCI bus (no timers yet) */
for (i = 0; i < 100 ; i++)
j = i + 1;
/* Now write the Base I/O Address Word to V3_BASE + 0x6C */
*(UINT16 *)(V3_BASE + V3_LB_IO_BASE) = (UINT16)(V3_BASE >> 16);
do
{
*(UINT8 *)(V3_BASE + V3_MAIL_DATA) = 0xAA;
*(UINT8 *)(V3_BASE + V3_MAIL_DATA + 4) = 0x55;
}
while (*(UINT8 *)(V3_BASE + V3_MAIL_DATA) != 0xAA ||
*(UINT8 *)(V3_BASE + V3_MAIL_DATA + 4) != 0x55);
/* Make sure that V3 register access is not locked, if it is, unlock it */
if ((*(UINT16 *)(V3_BASE + V3_SYSTEM) & V3_SYSTEM_M_LOCK) ==
V3_SYSTEM_M_LOCK)
*(UINT16 *)(V3_BASE + V3_SYSTEM) = 0xA05F;
/*
* Ensure that the slave accesses from PCI are disabled while we
* setup windows
*/
*(UINT16 *)(V3_BASE + V3_PCI_CMD) &=
~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN);
/* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */
*(UINT16 *)(V3_BASE + V3_SYSTEM) &= ~V3_SYSTEM_M_RST_OUT;
/* Make all accesses from PCI space retry until we're ready for them */
*(UINT16 *)(V3_BASE + V3_PCI_CFG) |= V3_PCI_CFG_M_RETRY_EN;
/*
* Set up any V3 PCI Configuration Registers that we absolutely have to
* LB_CFG controls Local Bus protocol.
* Enable LocalBus byte strobes for READ accesses too.
* set bit 7 BE_IMODE and bit 6 BE_OMODE
*/
*(UINT16 *)(V3_BASE + V3_LB_CFG) |= 0x0C0;
/*
* PCI_CMD controls overall PCI operation.
* Enable PCI bus master.
*/
*(UINT16 *)(V3_BASE + V3_PCI_CMD) |= 0x04;
/*
* PCI_MAP0 controls where the PCI to CPU memory window is on the Local Bus
*/
*(UINT32 *)(V3_BASE + V3_PCI_MAP0) = (INTEGRATOR_BOOT_ROM_BASE) |
(V3_PCI_MAP_M_ADR_SIZE_512M |
V3_PCI_MAP_M_REG_EN |
V3_PCI_MAP_M_ENABLE);
/* PCI_BASE0 is the PCI address of the start of the window */
*(UINT32 *)(V3_BASE + V3_PCI_BASE0) = INTEGRATOR_BOOT_ROM_BASE;
/* PCI_MAP1 is LOCAL address of the start of the window */
*(UINT32 *)(V3_BASE + V3_PCI_MAP1) = (INTEGRATOR_HDR0_SDRAM_BASE) |
(V3_PCI_MAP_M_ADR_SIZE_1024M | V3_PCI_MAP_M_REG_EN |
V3_PCI_MAP_M_ENABLE);
/* PCI_BASE1 is the PCI address of the start of the window */
*(UINT32 *)(V3_BASE + V3_PCI_BASE1) = INTEGRATOR_HDR0_SDRAM_BASE;
/*
* Set up the windows from local bus memory into PCI configuration,
* I/O and Memory.
* PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this.
*/
*(UINT16 *)(V3_BASE +V3_LB_BASE2) =
((CPU_PCI_IO_ADRS >> 24) << 8) | V3_LB_BASE_M_ENABLE;
*(UINT16 *)(V3_BASE + V3_LB_MAP2) = 0;
/*
* PCI Configuration, use LB_BASE1/LB_MAP1.
*
* PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1
* Map first 256Mbytes as non-prefetchable via BASE0/MAP0
* (INTEGRATOR_PCI_BASE == PCI_MEM_BASE)
*/
*(UINT32 *)(V3_BASE + V3_LB_BASE0) =
INTEGRATOR_PCI_BASE | (0x80 | V3_LB_BASE_M_ENABLE);
*(UINT16 *)(V3_BASE + V3_LB_MAP0) =
((INTEGRATOR_PCI_BASE >> 20) << 0x4) | 0x0006;
/* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */
*(UINT32 *)(V3_BASE + V3_LB_BASE1) =
INTEGRATOR_PCI_BASE | (0x84 | V3_LB_BASE_M_ENABLE);
*(UINT16 *)(V3_BASE + V3_LB_MAP1) =
(((INTEGRATOR_PCI_BASE + SZ_256M) >> 20) << 4) | 0x0006;
/*
* Allow accesses to PCI Configuration space
* and set up A1, A0 for type 1 config cycles
*/
*(UINT16 *)(V3_BASE + V3_PCI_CFG) = ((*(UINT16 *)(V3_BASE + V3_PCI_CFG)) &
~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1) ) |
V3_PCI_CFG_M_AD_LOW0;
/* now we can allow in PCI MEMORY accesses */
*(UINT16 *)(V3_BASE + V3_PCI_CMD) =
(*(UINT16 *)(V3_BASE + V3_PCI_CMD)) | V3_COMMAND_M_MEM_EN;
/*
* Set RST_OUT to take the PCI bus is out of reset, PCI devices can
* initialise and lock the V3 system register so that no one else
* can play with it
*/
*(UINT16 *)(V3_BASE + V3_SYSTEM) =
(*(UINT16 *)(V3_BASE + V3_SYSTEM)) | V3_SYSTEM_M_RST_OUT;
*(UINT16 *)(V3_BASE + V3_SYSTEM) =
(*(UINT16 *)(V3_BASE + V3_SYSTEM)) | V3_SYSTEM_M_LOCK;
return;
}
#endif /* defined(INCLUDE_PCI) */
void sysSerialHwInit4(void)
{
/*ambaChan[0].sio.pDrvFuncs->ioctl*//*ambaIoctl(&(ambaChan[0].sio),SIO_MODE_SET,SIO_MODE_POLL);*/
}
void bootPrintStar(void)
{
SIO_CHAN * pSioChan;
pSioChan = sysSerialChanGet ( 0 );
sioPollOutput(pSioChan, '*');
/*ambaPollOutput(&(ambaChan[0].sio), '*');*/
}
void bootPrint(char *msg)
{
SIO_CHAN * pSioChan;
int msgIx ;
int len = strlen(msg);
pSioChan = sysSerialChanGet ( 0 );
for ( msgIx = 0; msgIx < len; msgIx++ )
{
while ( sioPollOutput ( pSioChan, msg[ msgIx ] ) == EAGAIN );
}
return;
}
char bootInput(void)
{
SIO_CHAN * pSioChan;
char msg;
pSioChan = sysSerialChanGet ( 0 );
while ( sioPollInput ( pSioChan, &msg ) == EAGAIN );
return msg;
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