primecellsio.h

ATMEL920T的BSP及ETH等已经设备驱动程序

/* ambaSio.h - ARM AMBA UART header file */

/* Copyright 1997 Wind River Systems, Inc. */

/*
modification history
--------------------
01b,21feb00,jpd  renamed primecell... symbols to primeCell...
01a,10nov99,ajb  Modified from ambaSio.h, version 01b.  Added support for
                 enabling interrupts in UART_CR.
*/

#ifndef __INCprimeCellSioh 
#define __INCprimeCellSioh 

#ifdef __cplusplus
extern "C" {
#endif

/* Register description OF ARM AMBA UART */

#ifndef _ASMLANGUAGE


/* Register offsets from base address */

/*#define	UARTDR		0x00		*//* UART data register (R/W) */
#define	UARTDR		0x1c		/* UART data register (W/O) */
#define	RXSTAT		0x04		/* Rx data status register (R/O) */
#define	UMSEOI		0x04		/* Clr modem status changed int (W/O) */
#define	H_UBRLCR	0x08		/* } High middle and low bytes (R/W) */
#define	M_UBRLCR	0x0C		/* } of bit rate and line (W/O) */
#define	L_UBRLCR	0x10		/* } register (W/O) */
/*#define	UARTCON		0x14		*//* control register (R/W) */
#define	UARTCON		0x0		/* control register (W/O) */
/*#define	UARTFLG		0x18		*//* FIFO status register (R/O) */
#define	UARTFLG		0x14		/* FIFO status register (R/O) */
#define UARTIIR		0x1C		/* Int identification reg (R/O) */
#define UARTICR		0x1C		/* Int clear register (W/O) */

#define DBGU_CR        		0x00			/* Control Register */
#define DBGU_MR        	0x04			/* Mode Register */
#define DBGU_IER        	0x08			/* Interrupt Enable Register */
#define DBGU_IDR        	0x0c			/* Interrupt Disable Register */
#define DBGU_IMR        	0x10 			/* Interrupt Mask Register */
#define DBGU_SR        		0x14 			/* Status Register */
#define DBGU_RHR        	0x18 			/* Receiver Holding Register*/
#define DBGU_THR        	0x1c 			/* Transmitter Holding Register*/
#define DBGU_BRGR        	0x20 			/* Baud Rate Generator Register*/
#define DBGU_TTGR       	0x28 			/* Timeguard Register*/

#define DBGU_PDC_RPR 		0x100 			/* Receive Pointer Register*/
#define DBGU_PDC_RCR		0x104 			/* Receive Counter Register*/
#define DBGU_PDC_TPR    		0x108 			/* Transmit Pointer Register*/
#define DBGU_PDC_TCR   		0x10c 			/* Transmit Counter Register*/
#define DBGU_PDC_RNPR    	0x110 			/* Receive Next Pointer Register*/
#define DBGU_PDC_RNCR    	0x114 			/* Receive Next Counter Register*/
#define DBGU_PDC_TNPR      	0x118 			/* Transmit Next Pointer Register*/
#define DBGU_PDC_TNCR     	0x11c 			/* Transmit Next Counter Register*/
#define DBGU_PDC_PTCR       	0x120 			/* PDC Transfer Control Register*/


/* bit definitions within H_UBRLCR register */

#define PARITY_NONE	0x00		/* set no parity */
#define ONE_STOP	0x00		/* set one stop bit */
#define FIFO_ENABLE	0x10		/* Enable both FIFOs */
#define WORD_LEN_5	(0x00 << 5)	/* Set UART word lengths */
#define WORD_LEN_6	(0x01 << 5)
#define WORD_LEN_7	(0x02 << 5)
#define WORD_LEN_8	(0x03 << 5)


/* bit definitions within UARTCR register */
/* old define,not used*/
#define UART_LBE	0x80		/* Loop Back Enable */
#define UART_RTIE 	0x40		/* Receive Timeout Int Enable */
#define UART_TIE	0x20		/* Transmit Int Enable */
#define UART_RIE	0x10		/* Receive Int Enable */
#define UART_MSIE	0x08		/* Modem Status Int Enable */
#define UART_ENABLE	0x01		/* Enable the UART */
/* new define*/	/*huxianpeng 20051230*/
#define DBGU_CR_RSTSTA	0x100	/* Reset FARE,FRAME,OVER bits in DBGU_SR*/
#define DBGU_CR_TXEN	0x40	/* Enable the Transmitter */ 	
#define DBGU_CR_TXDIS	0x80	/* Disable the Transmitter */ 	
#define DBGU_CR_RXEN	0x10	/* Enable the Receiver */ 
#define DBGU_CR_RXDIS	0x20	/* Disable the Receiver */ 
#define DBGU_CR_RSTTX	0x08	/* Reset and Disable the Transmitter logic */ 
#define DBGU_CR_RSTRX	0x04	/* Reset and Disable the Receiver logic */ 

/* bit definitions within UARTFR register */

#define FLG_UTXFE	(0x01 << 7)	/* UART Tx FIFO Empty */
#define FLG_URXFF	(0x01 << 6)	/* UART Rx FIFO Full */
/*#define FLG_UTXFF	(0x01 << 5)	*//* UART Tx FIFO Full */
#define FLG_UTXFF	(0x01 << 1)	/* UART Tx FIFO Full */
/*#define FLG_URXFE	(0x01 << 4)	*//* UART Rx FIFO Empty */
#define FLG_URXFE	(0x01 << 0)	/* UART Rx FIFO Empty */

/* bit definitions within UARTIIR/ICR register */

#define UART_RTIS	0x08		/* Receive Timeout Int Status */
#define UART_TIS	0x04		/* Transmit Int Status */
#define UART_RIS	0x02		/* Receive Int Status */
#define UART_MIS	0x01		/* Modem Int Status */

/* bit definitions within DBGU_IER register */ /*huxianpeng 20051230*/
#define DBGU_IER_RXRDY		0x00000001	/* Enable RXRDY Interrupt*/
#define DBGU_IER_TXRDY		0x00000002	/* Enable TXRDY Interrupt*/
#define DBGU_IER_ENDRX		0x00000004	/* Enable End of Receive Transfer  Interrupt*/
#define DBGU_IER_ENDTX		0x00000010	/* Enable End of Transmit  Interrupt*/
#define DBGU_IER_OVER		0x00000020	/* Enable Overrun Error Interrupt*/
#define DBGU_IER_FRAME		0x00000040	/* Enable Framing Error Interrupt*/
#define DBGU_IER_PARE		0x00000080	/* Enable Parity Error Interrupt*/
#define DBGU_IER_TXEMPTY	0x00000200	/* Enable TXEMPTY Interrupt*/
#define DBGU_IER_TXBUFE	0x00000800	/* Enable Buffer Empty Interrupt*/
#define DBGU_IER_RXBUFF	0x00001000	/* Enable Buffer Full Interrupt*/
#define DBGU_IER_COMMTX	0x40000000	/* Enable COMMTX (from ARM) Interrupt*/
#define DBGU_IER_COMMRX	0x80000000	/* Enable COMMRX (from ARM) Interrupt*/

/* bit definitions within Debug Unit Mode Register*/
#define 	AT91C_US_PAR              			(0x7 <<  9) /* (DBGU) Parity type*/
#define 	AT91C_US_PAR_EVEN                 	(0x0 <<  9) /* (DBGU) Even Parity*/
#define 	AT91C_US_PAR_ODD                  	(0x1 <<  9) /* (DBGU) Odd Parity*/
#define 	AT91C_US_PAR_SPACE                	(0x2 <<  9) /* (DBGU) Parity forced to 0 (Space)*/
#define 	AT91C_US_PAR_MARK                 	(0x3 <<  9) /* (DBGU) Parity forced to 1 (Mark)*/
#define 	AT91C_US_PAR_NONE                 	(0x4 <<  9) /* (DBGU) No Parity*/
#define 	AT91C_US_PAR_MULTI_DROP         (0x6 <<  9) /* (DBGU) Multi-drop mode*/
#define 	AT91C_US_CHMODE           		(0x3 << 14) /* (DBGU) Channel Mode*/
#define 	AT91C_US_CHMODE_NORMAL        	(0x0 << 14) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.*/
#define 	AT91C_US_CHMODE_AUTO              (0x1 << 14) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.*/
#define 	AT91C_US_CHMODE_LOCAL             (0x2 << 14) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.*/
#define 	AT91C_US_CHMODE_REMOTE          (0x3 << 14) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.*/




typedef struct AMBA_CHAN
    {
    /* must be first */

    SIO_CHAN	sio;		/* standard SIO_CHAN element */

    /* callbacks */

    STATUS	(*getTxChar) ();  /* installed Tx callback routine */
    STATUS	(*putRcvChar) (); /* installed Rx callback routine */
    void *	getTxArg;	/* argument to Tx callback routine */
    void *	putRcvArg;	/* argument to Rx callback routine */

    UINT32 *	regs;		/* AMBA registers */
    UINT8 	levelRx;	/* Rx Interrupt level for this device */
    UINT8 	levelTx;	/* Tx Interrupt level for this device */

    UINT32	channelMode;	/* such as INT, POLL modes */
    int		baudRate;	/* the current baud rate */
    UINT32	xtal;		/* UART clock frequency */     

    } AMBA_CHAN;


/* function declarations */

extern void primeCellSioInt (AMBA_CHAN *pChan);
extern void primeCellSioIntTx (AMBA_CHAN *pChan);
extern void primeCellSioIntRx (AMBA_CHAN *pChan);
extern void primeCellSioDevInit (AMBA_CHAN *pChan);
extern void  comOutputTest( char outChar );
#endif	/* _ASMLANGUAGE */

#ifdef __cplusplus
}
#endif
 
#endif /* __INCprimeCellSioh */