integrator.h

ATMEL920T的BSP及ETH等已经设备驱动程序

#define INT_PRI_PIOC				3
#define INT_PRI_PIOD				3
#define INT_PRI_US0					0
#define INT_PRI_US1					0
#define INT_PRI_US2					0
#define INT_PRI_US3					0
#define INT_PRI_MCI					1
#define INT_PRI_UDP					0
#define INT_PRI_TWI					1
#define INT_PRI_SPI					1
#define INT_PRI_SSC0				1
#define INT_PRI_SSC1				1
#define INT_PRI_SSC2				1
#define INT_PRI_TC0					2
#define INT_PRI_TC1					2
#define INT_PRI_TC2					2
#define INT_PRI_TC3					2
#define INT_PRI_TC4					2
#define INT_PRI_TC5					2
#define INT_PRI_UHP					0
#define INT_PRI_EMAC				5
#define INT_PRI_IRQ0				4
#define INT_PRI_IRQ1				4
#define INT_PRI_IRQ2				4
#define INT_PRI_IRQ3				4
#define INT_PRI_IRQ4				4
#define INT_PRI_IRQ5				4
#define INT_PRI_IRQ6				4





/* definitions for the AMBA UART */

#define UART_XTAL_FREQ		INTEGRATOR_UARTCLK /* UART baud rate clk freq */
#define N_SIO_CHANNELS		N_AMBA_UART_CHANNELS
#define N_UART_CHANNELS		N_AMBA_UART_CHANNELS
/*#define N_AMBA_UART_CHANNELS	2		*//* number of AMBA UART chans */
#define N_AMBA_UART_CHANNELS	1		/* number of AMBA UART chans */
/*#define UART_0_BASE_ADR		0x16000000	*//* UART 0 base address */
#define UART_0_BASE_ADR		AT91C_BASE_DBGU	/* UART 0 base address */
/*#define UART_1_BASE_ADR		0x17000000	*//* UART 1 base address */
#define UART_1_BASE_ADR		AT91C_BASE_DBGU	/* UART 1 base address */

/* definitions for the keyboard */
#define KBD_BASE_ADR		0x18000000	/* Keyboard 0 base address */
#define MOUSE_BASE_ADR		0x19000000	/* Mouse 1 base address */

#define KBD_REGS_SIZE           0x14
#define MOUSE_REGS_SIZE         0x14

/* definitions for the AMBA Timer */

/*#define AMBA_TIMER_BASE		0x13000000	*//* Address of base of timer */
#define AMBA_TIMER_BASE		AT91C_BASE_ST	/* base Address of System timer */
#define AMBA_BASE_OFFSET        0X100
#define AT91_ST_CR				AMBA_TIMER_BASE+0x00	/*	Control Register 	*//*Write*/
#define AT91_ST_PIMR			AMBA_TIMER_BASE+0x04	/*	Period Interval Mode Register 	*//*Read/Write*/
#define AT91_ST_WDMR			AMBA_TIMER_BASE+0x08	/*	Watch Dog Mode Register 	*/	/*Read/Write*/
#define AT91_ST_RTMR			AMBA_TIMER_BASE+0x0c	/*	Real-Time Mode Register 	*//*Read/Write*/
#define AT91_ST_SR				AMBA_TIMER_BASE+0x10	/*	Status Register 	*//*Read */
#define AT91_ST_IER				AMBA_TIMER_BASE+0x14	/*	Interrupt Enable Register 	*//*Write*/
#define AT91_ST_IDR				AMBA_TIMER_BASE+0x18	/*	Interrupt Disable Register 	*//*Write*/
#define AT91_ST_IMR				AMBA_TIMER_BASE+0x1c	/*	Interrupt Mask Register 	*//*Read */
#define AT91_ST_RTAR			AMBA_TIMER_BASE+0x20	/*	Real-Time Alarm Register 	*//*Read/Write*/
#define AT91_ST_CRTR			AMBA_TIMER_BASE+0x24	/*	Current Real-Time Register 	*//*Read */

#define ST_bSet_ALMS			1<<3	/*	Alarm Status Interrupt bit*/ 
#define ST_bSet_RTTINC			1<<2	/*	Real-Time Increment  Interrupt bit*/ 
#define ST_bSet_WDOVF			1<<1	/*	Watchdog Overflow Interrupt bit*/ 
#define ST_bSet_PITS				1<<0	/*	Period Interval Timer Status Interrupt bit*/ 


#define AMBA_TIMER0_BASE ((AMBA_TIMER_BASE))
#define AMBA_TIMER1_BASE ((AMBA_TIMER_BASE) + AMBA_BASE_OFFSET)
#define AMBA_TIMER2_BASE ((AMBA_TIMER_BASE) + 2 * AMBA_BASE_OFFSET)

#define SYS_TIMER_BASE AMBA_TIMER0_BASE
#define AUX_TIMER_BASE AMBA_TIMER1_BASE

#define SYS_TIMER_INT_LVL (INT_LVL_TIMER_0)
#define AUX_TIMER_INT_LVL (INT_LVL_TIMER_1)

/* Add corresponding INT_VEC definitions for intConnect calls. */

#define SYS_TIMER_INT_VEC (INT_VEC_TIMER_0)
#define AUX_TIMER_INT_VEC (INT_VEC_TIMER_1)

#define AMBA_TIMER_SYS_TC_DISABLE	(TC_DISABLE | TC_PERIODIC | TC_DIV16)
#define AMBA_TIMER_SYS_TC_ENABLE	(TC_ENABLE  | TC_PERIODIC | TC_DIV16)
#define AMBA_TIMER_AUX_TC_DISABLE	(TC_DISABLE | TC_PERIODIC | TC_DIV16)
#define AMBA_TIMER_AUX_TC_ENABLE	(TC_ENABLE  | TC_PERIODIC | TC_DIV16)

/* Frequency of counter/timers */

#define SYS_TIMER_CLK	(INTEGRATOR_SYSCLK/16)
#define AUX_TIMER_CLK	(INTEGRATOR_CLK24MHZ/16)

#define AMBA_RELOAD_TICKS	0	/* No overhead */

/* Mask out unused bits from timer register. */

#define AMBA_TIMER_VALUE_MASK	0xFFFF

/* Sys Clk is timer 1 */

#define SYS_TIMER_CLEAR AMBA_TIMER_T1CLEAR
#define SYS_TIMER_CTRL  AMBA_TIMER_T1CTRL
#define SYS_TIMER_LOAD  AMBA_TIMER_T1LOAD
#define SYS_TIMER_VALUE AMBA_TIMER_T1VALUE

/* Aux Clk is timer 2 */

#define AUX_TIMER_CLEAR AMBA_TIMER_T2CLEAR
#define AUX_TIMER_CTRL  AMBA_TIMER_T2CTRL
#define AUX_TIMER_LOAD  AMBA_TIMER_T2LOAD
#define AUX_TIMER_VALUE AMBA_TIMER_T2VALUE


/*
 * Clock rates depend upon CPU power and work load of application.
 * The values below are minimum and maximum allowed by the hardware.
 * So:
 * min frequency = roundup(clock_rate/(max_counter_value))
 * max frequency = rounddown(clock_rate/(min_counter_value))
 * i.e. SYS_CLK_RATE_MAX = SYS_TIMER_CLK
 *      AUX_CLK_RATE_MAX = AUX_TIMER_CLK
 *
 * However, we must set maxima that are sustainable on a running
 * system determined by experimentation.
 *
 * The 720T values have been determined by experimentation, the others
 * need to be checked.
 */

#define SYS_CLK_RATE_MIN ((SYS_TIMER_CLK+0xFFFF)/0x10000)
#if defined(CPU_720T) || defined(CPU_720T_T)
#define SYS_CLK_RATE_MAX 25000
#elif defined(CPU_740T) || defined(CPU_740T_T)
#define SYS_CLK_RATE_MAX 25000
#elif defined(CPU_920T) || defined(CPU_920T_T)
#define SYS_CLK_RATE_MAX 25000
#elif defined(CPU_940T) || defined(CPU_940T_T)
#define SYS_CLK_RATE_MAX 25000
#elif defined(CPU_946ES) || defined(CPU_946ES_T)
#define SYS_CLK_RATE_MAX 25000
#elif defined(CPU_966ES) || defined(CPU_966ES_T)
#define SYS_CLK_RATE_MAX 6000
#else
#define SYS_CLK_RATE_MAX 9000
#endif

#define AUX_CLK_RATE_MIN ((AUX_TIMER_CLK+0xFFFF)/0x10000)
#if defined(CPU_720T) || defined(CPU_720T_T)
#define AUX_CLK_RATE_MAX 25000
#elif defined(CPU_740T) || defined(CPU_740T_T)
#define AUX_CLK_RATE_MAX 25000
#elif defined(CPU_920T) || defined(CPU_920T_T)
#define AUX_CLK_RATE_MAX 25000
#elif defined(CPU_940T) || defined(CPU_940T_T)
#define AUX_CLK_RATE_MAX 25000
#elif defined(CPU_946ES) || defined(CPU_946ES_T)
#define AUX_CLK_RATE_MAX 25000
#elif defined(CPU_966ES) || defined(CPU_966ES_T)
#define AUX_CLK_RATE_MAX 6000
#else
#define AUX_CLK_RATE_MAX 9000
#endif


/* PCI definitions */

/* Interrupt number for PCI */

#define INT_NUM_IRQ0	INT_LVL_PCI_0

/* V3 PCI bridge controller */

#define V3_BASE		0x62000000    /* V360EPC registers */

/* Bit field definitions */

#define BIT0                            0x00000001
#define BIT1                            0x00000002
#define BIT2                            0x00000004
#define BIT3                            0x00000008
#define BIT4                            0x00000010
#define BIT5                            0x00000020
#define BIT6                            0x00000040
#define BIT7                            0x00000080
#define BIT8                            0x00000100
#define BIT9                            0x00000200
#define BIT10                           0x00000400
#define BIT11                           0x00000800
#define BIT12                           0x00001000
#define BIT13                           0x00002000
#define BIT14                           0x00004000
#define BIT15                           0x00008000
#define BIT16                           0x00010000
#define BIT17                           0x00020000
#define BIT18                           0x00040000
#define BIT19                           0x00080000
#define BIT20                           0x00100000

/* Handy sizes */

#define SZ_1K                           0x00000400
#define SZ_4K                           0x00001000
#define SZ_8K                           0x00002000
#define SZ_16K                          0x00004000
#define SZ_64K                          0x00010000
#define SZ_128K                         0x00020000
#define SZ_256K                         0x00040000
#define SZ_512K                         0x00080000

#define SZ_1M                           0x00100000
#define SZ_2M                           0x00200000
#define SZ_4M                           0x00400000
#define SZ_8M                           0x00800000
#define SZ_16M                          0x01000000
#define SZ_32M                          0x02000000
#define SZ_64M                          0x04000000
#define SZ_128M                         0x08000000
#define SZ_256M                         0x10000000
#define SZ_512M                         0x20000000

#define SZ_1G                           0x40000000
#define SZ_2G                           0x80000000


/* V3 Local Bus to PCI Bridge definitions */

#define V3_PCI_VENDOR                   0x00000000
#define V3_PCI_DEVICE                   0x00000002
#define V3_PCI_CMD                      0x00000004
#define V3_PCI_STAT                     0x00000006
#define V3_PCI_CC_REV                   0x00000008
#define V3_PCI_HDR_CFG                  0x0000000C
#define V3_PCI_IO_BASE                  0x00000010
#define V3_PCI_BASE0                    0x00000014
#define V3_PCI_BASE1                    0x00000018
#define V3_PCI_SUB_VENDOR               0x0000002C
#define V3_PCI_SUB_ID                   0x0000002E
#define V3_PCI_ROM                      0x00000030
#define V3_PCI_BPARAM                   0x