integrator.h

ATMEL920T的BSP及ETH等已经设备驱动程序

#define INTEGRATOR_EBI_32_BIT           0x02
#define INTEGRATOR_EBI_WRITE_ENABLE     0x04
#define INTEGRATOR_EBI_SYNC             0x08
#define INTEGRATOR_EBI_WS_2             0x00
#define INTEGRATOR_EBI_WS_3             0x10
#define INTEGRATOR_EBI_WS_4             0x20
#define INTEGRATOR_EBI_WS_5             0x30
#define INTEGRATOR_EBI_WS_6             0x40
#define INTEGRATOR_EBI_WS_7             0x50
#define INTEGRATOR_EBI_WS_8             0x60
#define INTEGRATOR_EBI_WS_9             0x70
#define INTEGRATOR_EBI_WS_10            0x80
#define INTEGRATOR_EBI_WS_11            0x90
#define INTEGRATOR_EBI_WS_12            0xA0
#define INTEGRATOR_EBI_WS_13            0xB0
#define INTEGRATOR_EBI_WS_14            0xC0
#define INTEGRATOR_EBI_WS_15            0xD0
#define INTEGRATOR_EBI_WS_16            0xE0
#define INTEGRATOR_EBI_WS_17            0xF0



/* System Controller */

#define INTEGRATOR_SC_ID_OFFSET		(0x00)
#define INTEGRATOR_SC_OSC_OFFSET	(0x04)
#define INTEGRATOR_SC_CTRLS_OFFSET	(0x08)
#define INTEGRATOR_SC_CTRLC_OFFSET	(0x0C)
#define INTEGRATOR_SC_DEC_OFFSET	(0x10)
#define INTEGRATOR_SC_ARB_OFFSET	(0x14)
#define INTEGRATOR_SC_PCIENABLE_OFFSET	(0x18)
#define INTEGRATOR_SC_LOCK_OFFSET	(0x1C)

#define INTEGRATOR_SC_BASE		(0x11000000)
#define INTEGRATOR_SC_ID \
			(INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET)
#define INTEGRATOR_SC_OSC \
			(INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET)
#define INTEGRATOR_SC_CTRLS \
			(INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
#define INTEGRATOR_SC_CTRLC \
			(INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
#define INTEGRATOR_SC_DEC \
			(INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET)
#define INTEGRATOR_SC_ARB \
			(INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET)
#define INTEGRATOR_SC_PCIENABLE \
			(INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
#define INTEGRATOR_SC_LOCK \
			(INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET)

#define INTEGRATOR_SC_OSC_SYS_10MHz	(0x20)
#define INTEGRATOR_SC_OSC_SYS_15MHz	(0x34)
#define INTEGRATOR_SC_OSC_SYS_20MHz	(0x48)
#define INTEGRATOR_SC_OSC_SYS_25MHz	(0x5C)
#define INTEGRATOR_SC_OSC_SYS_33MHz	(0x7C)
#define INTEGRATOR_SC_OSC_SYS_MASK	(0xFF)

#define INTEGRATOR_SC_OSC_PCI_25MHz	(0x100)
#define INTEGRATOR_SC_OSC_PCI_33MHz	(0x0)
#define INTEGRATOR_SC_OSC_PCI_MASK	(0x100)

#define FL_SC_CONTROL			0x06	/* Enable Flash Write and Vpp */


/* - Hard coded id of the core module we are compiling for. */

#define CORE_MODULE 0

/*
 * interrupt control stuff
 * Note: FIQ is not handled within VxWorks so this is just IRQ
 */

#define IC_BASE 		AT91C_BASE_AIC
#define IRQ_STATUS	(IC_BASE+0x108)	/* Read */
#define IRQ_RAW_STATUS	(IC_BASE+0x10C)	/* Read */
#define IRQ_ENABLE	(IC_BASE+0x120)	/* Write */
#define IRQ_DISABLE	(IC_BASE+0x124)	/* Write */
/*#define IRQ_SOFT	(IC_BASE+0x12C)	*//* Read/Write */
/*#define IRQ_SOFTCLR     (IC_BASE+0x128) *//* Write */
/*#define FIQ_STATUS	(IC_BASE+0x108)*/	/* Read */
/*#define FIQ_RAW_STATUS	(IC_BASE+0x10C)*/	/* Read */
/*#define FIQ_ENABLE	(IC_BASE+0x120)	*//* Read/Write */
/*#define FIQ_DISABLE	(IC_BASE+0x124)	*//* Write */

/*#define IC_BASE 	(0x14000000 + (CORE_MODULE * 0x40))*/
/*#define IRQ_STATUS	(IC_BASE+0x000)	*//* Read */
/*#define IRQ_RAW_STATUS	(IC_BASE+0x004)	*//* Read */
/*#define IRQ_ENABLE	(IC_BASE+0x008)	 *//* Read/Write */
/*#define IRQ_DISABLE	(IC_BASE+0x00C)	*//* Write */
#define IRQ_SOFT	(IC_BASE+0x010)	/* Read/Write */
#define IRQ_SOFTCLR     (IC_BASE+0x014) /* Write */
#define FIQ_STATUS	(IC_BASE+0x020)	/* Read */
#define FIQ_RAW_STATUS	(IC_BASE+0x024)	/* Read */
#define FIQ_ENABLE	(IC_BASE+0x028)	/* Read/Write */
#define FIQ_DISABLE	(IC_BASE+0x02C)  /* Write */

#define AT91_AIC_IVR		(IC_BASE+0x100)		/* Interrupt Vector Register */	/* Read*/
#define AT91_AIC_FVR		(IC_BASE+0x104)		/* Fast Interrupt Vector Register */	/* Read*/
#define AT91_AIC_ISR		(IC_BASE+0x108)		/* Interrupt Status Register */	/* Read*/
#define AT91_AIC_IPR		(IC_BASE+0x10c)		/* Interrupt Pending Register */	/* Read*/
#define AT91_AIC_IMR		(IC_BASE+0x110)		/* Interrupt Mask Register */	/* Read*/
#define AT91_AIC_CISR		(IC_BASE+0x114)		/* Core Interrupt Status Register */	/* Read*/
#define AT91_AIC_IECR		(IC_BASE+0x120)		/* Interrupt Enable Command Register */	/* Write*/
#define AT91_AIC_IDCR		(IC_BASE+0x124)		/* Interrupt Disable Command Register */	/* Write*/
#define AT91_AIC_ICCR		(IC_BASE+0x128)		/* Interrupt Clear Command Register */	/* Write*/
#define AT91_AIC_ISCR		(IC_BASE+0x12c)		/* Interrupt Set Command Register */	/* Write*/
#define AT91_AIC_EOICR		(IC_BASE+0x130)		/* End of Interrupt Command Register */	/* Write*/
#define AT91_AIC_SPU		(IC_BASE+0x134)		/* Superius Interrupt Vector Register */	/* Read/Write*/
#define AT91_AIC_DCR		(IC_BASE+0x138)		/* Debug Control Register */	/* Read/Write*/

/*#define AMBA_INT_NUM_LEVELS	22*/
#define AMBA_INT_NUM_LEVELS	32	/* 32 interrupt source for AT91RM9200 */
/*#define AMBA_INT_CSR_PEND	IRQ_STATUS*/
#define AMBA_INT_CSR_PEND	IRQ_RAW_STATUS
#define AMBA_INT_CSR_ENB	IRQ_ENABLE
#define AMBA_INT_CSR_DIS	IRQ_DISABLE
/*#define AMBA_INT_CSR_MASK	0x003FFFFF *//* Mask out invalid status bits */
#define AMBA_INT_CSR_MASK	0xFFFFFFFF /* Mask out invalid status bits */

/* Interrupt levels */

#define INT_LVL_SOFT		0	/* soft interrupt */
#define INT_LVL_UART_0  	1	/* UART 0 */
#define INT_LVL_UART_1		2	/* UART 1 */
#define INT_LVL_KEYBOARD	3	/* keyboard interrupt */
#define INT_LVL_MOUSE		4	/* mouse interrupt */
#define INT_LVL_TIMER_0		5	/* timer 0 */
#define INT_LVL_TIMER_1		6	/* timer 1 */
#define INT_LVL_TIMER_2		7	/* timer 2 */
#define INT_LVL_RTC		8	/* real-time clock */
#define INT_LVL_EXP0		9	/* logic module 0 */
#define INT_LVL_EXP1		10	/* logic module 1 */
#define INT_LVL_EXP2		11	/* logic module 2 */
#define INT_LVL_EXP3		12	/* logic module 3 */
#define INT_LVL_PCI_0		13	/* PCI int A */
#define INT_LVL_PCI_1		14	/* PCI int B */
#define INT_LVL_PCI_2		15	/* PCI int C */
#define INT_LVL_PCI_3		16	/* PCI int D */
#define INT_LVL_PCIBRIDGE	17	/* V3 PCI bridge interrupt */
#define INT_LVL_DEG		18	/* CompactPCI aux (DEG#) */
#define INT_LVL_ENUM		19	/* CompactPCI aux (ENUM#) */
#define INT_LVL_PCILB		20	/* PCI local bus fault */
#define INT_LVL_APC		21	/* AutoPC external int */

/* interrupt vectors */

#define INT_VEC_SOFT		IVEC_TO_INUM(INT_LVL_SOFT)
#define INT_VEC_UART_0		IVEC_TO_INUM(INT_LVL_UART_0)
#define INT_VEC_UART_1		IVEC_TO_INUM(INT_LVL_UART_1)
#define INT_VEC_KEYBOARD	IVEC_TO_INUM(INT_LVL_KEYBOARD)
#define INT_VEC_MOUSE		IVEC_TO_INUM(INT_LVL_MOUSE)
#define INT_VEC_TIMER_0		IVEC_TO_INUM(INT_LVL_TIMER_0)
#define INT_VEC_TIMER_1		IVEC_TO_INUM(INT_LVL_TIMER_1)
#define INT_VEC_TIMER_2		IVEC_TO_INUM(INT_LVL_TIMER_2)
#define INT_VEC_RTC		IVEC_TO_INUM(INT_LVL_RTC)
#define INT_VEC_EXP0		IVEC_TO_INUM(INT_LVL_EXP0)
#define INT_VEC_EXP1		IVEC_TO_INUM(INT_LVL_EXP1)
#define INT_VEC_EXP2		IVEC_TO_INUM(INT_LVL_EXP2)
#define INT_VEC_EXP3		IVEC_TO_INUM(INT_LVL_EXP3)
#define INT_VEC_PCI_0		IVEC_TO_INUM(INT_LVL_PCI_0)
#define INT_VEC_PCI_1		IVEC_TO_INUM(INT_LVL_PCI_1)
#define INT_VEC_PCI_2		IVEC_TO_INUM(INT_LVL_PCI_2)
#define INT_VEC_PCI_3		IVEC_TO_INUM(INT_LVL_PCI_3)
#define INT_VEC_PCIBRIDGE	IVEC_TO_INUM(INT_LVL_PCIBRIDGE)
#define INT_VEC_DEG		IVEC_TO_INUM(INT_LVL_DEG)
#define INT_VEC_ENUM		IVEC_TO_INUM(INT_LVL_ENUM)
#define INT_VEC_PCILB		IVEC_TO_INUM(INT_LVL_PCILB)
#define INT_VEC_APC		IVEC_TO_INUM(INT_LVL_APC)


/*  interrupt source for AT91RM9200 */
#define INT_SRC_FIQ					0		/*	Advanced Interrupt Controller 	ID0 External*/
#define INT_SRC_SYSIRQ				1		/*	System Interrupt		ID1*/
#define INT_SRC_PIOA				2		/*	Parallel I/O Controller A	ID2*/
#define INT_SRC_PIOB				3		/*	Parallel I/O Controller B	ID3*/
#define INT_SRC_PIOC				4		/*	Parallel I/O Controller C	ID4*/
#define INT_SRC_PIOD				5		/*	Parallel I/O Controller D	ID5*/
#define INT_SRC_US0					6		/*	USART 0		ID6*/
#define INT_SRC_US1					7		/*	USART 1		ID7*/
#define INT_SRC_US2					8		/*	USART 2		ID8*/
#define INT_SRC_US3					9		/*	USART 3		ID9*/
#define INT_SRC_MCI					10		/*	Multimedia Card Interface	ID10*/
#define INT_SRC_UDP					11		/*	USB Device Port			ID11*/
#define INT_SRC_TWI					12		/*	Two-wire Interface			ID12*/
#define INT_SRC_SPI					13		/*	Serial Peripheral Interface	ID13*/
#define INT_SRC_SSC0				14		/*	Synchronous Serial Controller 0	ID14*/
#define INT_SRC_SSC1				15		/*	Synchronous Serial Controller 1	ID15*/
#define INT_SRC_SSC2				16		/*	Synchronous Serial Controller 2	ID16*/
#define INT_SRC_TC0					17		/*	Timer/Counter 0		ID17*/
#define INT_SRC_TC1					18		/*	Timer/Counter 1		ID18*/
#define INT_SRC_TC2					19		/*	Timer/Counter 2		ID19*/
#define INT_SRC_TC3					20		/*	Timer/Counter 3		ID20*/
#define INT_SRC_TC4					21		/*	Timer/Counter 4		ID21*/
#define INT_SRC_TC5					22		/*	Timer/Counter 5		ID22*/
#define INT_SRC_UHP					23		/*	USB Host Port			ID23*/
#define INT_SRC_EMAC				24		/*	Ethernet MAC			ID24*/
#define INT_SRC_IRQ0				25		/*	Advanced Interrupt Controller	ID25	External*/
#define INT_SRC_IRQ1				26		/*	Advanced Interrupt Controller	ID26	External*/
#define INT_SRC_IRQ2				27		/*	Advanced Interrupt Controller	ID27	External*/
#define INT_SRC_IRQ3				28		/*	Advanced Interrupt Controller	ID28	External*/
#define INT_SRC_IRQ4				29		/*	Advanced Interrupt Controller	ID29	External*/
#define INT_SRC_IRQ5				30		/*	Advanced Interrupt Controller	ID30	External*/
#define INT_SRC_IRQ6				31		/*	Advanced Interrupt Controller	ID31	External*/

/* interrupt vectors  for AT91RM9200*/
#define INT_VEC_FIQ					IVEC_TO_INUM(INT_SRC_FIQ)
#define INT_VEC_SYSIRQ				IVEC_TO_INUM(INT_SRC_SYSIRQ)
#define INT_VEC_PIOA				IVEC_TO_INUM(INT_SRC_PIOA)
#define INT_VEC_PIOB				IVEC_TO_INUM(INT_SRC_PIOB)
#define INT_VEC_PIOC				IVEC_TO_INUM(INT_SRC_PIOC)
#define INT_VEC_PIOD				IVEC_TO_INUM(INT_SRC_PIOD)
#define INT_VEC_US0					IVEC_TO_INUM(INT_SRC_US0)
#define INT_VEC_US1					IVEC_TO_INUM(INT_SRC_US1)
#define INT_VEC_US2					IVEC_TO_INUM(INT_SRC_US2)
#define INT_VEC_US3					IVEC_TO_INUM(INT_SRC_US3)
#define INT_VEC_MCI					IVEC_TO_INUM(INT_SRC_MCI)
#define INT_VEC_UDP					IVEC_TO_INUM(INT_SRC_UDP)
#define INT_VEC_TWI					IVEC_TO_INUM(INT_SRC_TWI)
#define INT_VEC_SPI					IVEC_TO_INUM(INT_SRC_SPI)
#define INT_VEC_SSC0				IVEC_TO_INUM(INT_SRC_SSC0)
#define INT_VEC_SSC1				IVEC_TO_INUM(INT_SRC_SSC1)
#define INT_VEC_SSC2				IVEC_TO_INUM(INT_SRC_SSC2)
#define INT_VEC_TC0					IVEC_TO_INUM(INT_SRC_TC0)
#define INT_VEC_TC1					IVEC_TO_INUM(INT_SRC_TC1)
#define INT_VEC_TC2					IVEC_TO_INUM(INT_SRC_TC2)
#define INT_VEC_TC3					IVEC_TO_INUM(INT_SRC_TC3)
#define INT_VEC_TC4					IVEC_TO_INUM(INT_SRC_TC4)
#define INT_VEC_TC5					IVEC_TO_INUM(INT_SRC_TC5)
#define INT_VEC_UHP					IVEC_TO_INUM(INT_SRC_UHP)
#define INT_VEC_EMAC				IVEC_TO_INUM(INT_SRC_EMAC)
#define INT_VEC_IRQ0				IVEC_TO_INUM(INT_SRC_IRQ0)
#define INT_VEC_IRQ1				IVEC_TO_INUM(INT_SRC_IRQ1)
#define INT_VEC_IRQ2				IVEC_TO_INUM(INT_SRC_IRQ2)
#define INT_VEC_IRQ3				IVEC_TO_INUM(INT_SRC_IRQ3)
#define INT_VEC_IRQ4				IVEC_TO_INUM(INT_SRC_IRQ4)
#define INT_VEC_IRQ5				IVEC_TO_INUM(INT_SRC_IRQ5)
#define INT_VEC_IRQ6				IVEC_TO_INUM(INT_SRC_IRQ6)

/* interrupt priority for AT91RM9200
     7 highest
     0 lowest
*/
#define INT_PRI_FIQ					7
#define INT_PRI_SYSIRQ				6
#define INT_PRI_PIOA				3
#define INT_PRI_PIOB				3