📄 integrator.h
字号:
#define AT91C_PIO_PD10 (1 << 10) /* Pin Controlled by PD10*/
#define AT91C_PD10_PCK3 (AT91C_PIO_PD10) /* PMC Programmable Clock Output 3*/
#define AT91C_PD10_TPS1 (AT91C_PIO_PD10) /* ETM ARM9 pipeline status 1*/
#define AT91C_PIO_PD11 (1 << 11) /* Pin Controlled by PD11*/
#define AT91C_PD11_ (AT91C_PIO_PD11) /* */
#define AT91C_PD11_TPS2 (AT91C_PIO_PD11) /* ETM ARM9 pipeline status 2*/
#define AT91C_PIO_PD12 (1 << 12) /* Pin Controlled by PD12*/
#define AT91C_PD12_ (AT91C_PIO_PD12) /* */
#define AT91C_PD12_TPK0 (AT91C_PIO_PD12) /* ETM Trace Packet 0*/
#define AT91C_PIO_PD13 (1 << 13) /* Pin Controlled by PD13*/
#define AT91C_PD13_ (AT91C_PIO_PD13) /* */
#define AT91C_PD13_TPK1 (AT91C_PIO_PD13) /* ETM Trace Packet 1*/
#define AT91C_PIO_PD14 (1 << 14) /* Pin Controlled by PD14*/
#define AT91C_PD14_ (AT91C_PIO_PD14) /* */
#define AT91C_PD14_TPK2 (AT91C_PIO_PD14) /* ETM Trace Packet 2*/
#define AT91C_PIO_PD15 (1 << 15) /* Pin Controlled by PD15*/
#define AT91C_PD15_TD0 (AT91C_PIO_PD15) /* SSC Transmit data*/
#define AT91C_PD15_TPK3 (AT91C_PIO_PD15) /* ETM Trace Packet 3*/
#define AT91C_PIO_PD16 (1 << 16) /* Pin Controlled by PD16*/
#define AT91C_PD16_TD1 (AT91C_PIO_PD16) /* SSC Transmit Data 1*/
#define AT91C_PD16_TPK4 (AT91C_PIO_PD16) /* ETM Trace Packet 4*/
#define AT91C_PIO_PD17 (1 << 17) /* Pin Controlled by PD17*/
#define AT91C_PD17_TD2 (AT91C_PIO_PD17) /* SSC Transmit Data 2*/
#define AT91C_PD17_TPK5 (AT91C_PIO_PD17) /* ETM Trace Packet 5*/
#define AT91C_PIO_PD18 (1 << 18) /* Pin Controlled by PD18*/
#define AT91C_PD18_NPCS1 (AT91C_PIO_PD18) /* SPI Peripheral Chip Select 1*/
#define AT91C_PD18_TPK6 (AT91C_PIO_PD18) /* ETM Trace Packet 6*/
#define AT91C_PIO_PD19 (1 << 19) /* Pin Controlled by PD19*/
#define AT91C_PD19_NPCS2 (AT91C_PIO_PD19) /* SPI Peripheral Chip Select 2*/
#define AT91C_PD19_TPK7 (AT91C_PIO_PD19) /* ETM Trace Packet 7*/
#define AT91C_PIO_PD2 (1 << 2) /* Pin Controlled by PD2*/
#define AT91C_PD2_ETX2 (AT91C_PIO_PD2) /* Ethernet MAC Transmit Data 2*/
#define AT91C_PIO_PD20 (1 << 20) /* Pin Controlled by PD20*/
#define AT91C_PD20_NPCS3 (AT91C_PIO_PD20) /* SPI Peripheral Chip Select 3*/
#define AT91C_PD20_TPK8 (AT91C_PIO_PD20) /* ETM Trace Packet 8*/
#define AT91C_PIO_PD21 (1 << 21) /* Pin Controlled by PD21*/
#define AT91C_PD21_RTS0 (AT91C_PIO_PD21) /* Usart 0 Ready To Send*/
#define AT91C_PD21_TPK9 (AT91C_PIO_PD21) /* ETM Trace Packet 9*/
#define AT91C_PIO_PD22 (1 << 22) /* Pin Controlled by PD22*/
#define AT91C_PD22_RTS1 (AT91C_PIO_PD22) /* Usart 0 Ready To Send*/
#define AT91C_PD22_TPK10 (AT91C_PIO_PD22) /* ETM Trace Packet 10*/
#define AT91C_PIO_PD23 (1 << 23) /* Pin Controlled by PD23*/
#define AT91C_PD23_RTS2 (AT91C_PIO_PD23) /* USART 2 Ready To Send*/
#define AT91C_PD23_TPK11 (AT91C_PIO_PD23) /* ETM Trace Packet 11*/
#define AT91C_PIO_PD24 (1 << 24) /* Pin Controlled by PD24*/
#define AT91C_PD24_RTS3 (AT91C_PIO_PD24) /* USART 3 Ready To Send*/
#define AT91C_PD24_TPK12 (AT91C_PIO_PD24) /* ETM Trace Packet 12*/
#define AT91C_PIO_PD25 (1 << 25) /* Pin Controlled by PD25*/
#define AT91C_PD25_DTR1 (AT91C_PIO_PD25) /* USART 1 Data Terminal ready*/
#define AT91C_PD25_TPK13 (AT91C_PIO_PD25) /* ETM Trace Packet 13*/
#define AT91C_PIO_PD26 (1 << 26) /* Pin Controlled by PD26*/
#define AT91C_PD26_TPK14 (AT91C_PIO_PD26) /* ETM Trace Packet 14*/
#define AT91C_PIO_PD27 (1 << 27) /* Pin Controlled by PD27*/
#define AT91C_PD27_TPK15 (AT91C_PIO_PD27) /* ETM Trace Packet 15*/
#define AT91C_PIO_PD3 (1 << 3) /* Pin Controlled by PD3*/
#define AT91C_PD3_ETX3 (AT91C_PIO_PD3) /* Ethernet MAC Transmit Data 3*/
#define AT91C_PIO_PD4 (1 << 4) /* Pin Controlled by PD4*/
#define AT91C_PD4_ETXEN (AT91C_PIO_PD4) /* Ethernet MAC Transmit Enable*/
#define AT91C_PIO_PD5 (1 << 5) /* Pin Controlled by PD5*/
#define AT91C_PD5_ETXER (AT91C_PIO_PD5) /* Ethernet MAC Transmikt Coding Error*/
#define AT91C_PIO_PD6 (1 << 6) /* Pin Controlled by PD6*/
#define AT91C_PD6_DTXD (AT91C_PIO_PD6) /* DBGU Debug Transmit Data*/
#define AT91C_PIO_PD7 (1 << 7) /* Pin Controlled by PD7*/
#define AT91C_PD7_PCK0 (AT91C_PIO_PD7) /* PMC Programmable Clock Output 0*/
#define AT91C_PD7_TSYNC (AT91C_PIO_PD7) /* ETM Synchronization signal*/
#define AT91C_PIO_PD8 (1 << 8) /* Pin Controlled by PD8*/
#define AT91C_PD8_PCK1 (AT91C_PIO_PD8) /* PMC Programmable Clock Output 1*/
#define AT91C_PD8_TCLK (AT91C_PIO_PD8) /* ETM Trace Clock signal*/
#define AT91C_PIO_PD9 (1 << 9) /* Pin Controlled by PD9*/
#define AT91C_PD9_PCK2 (AT91C_PIO_PD9) /* PMC Programmable Clock 2*/
#define AT91C_PD9_TPS0 (AT91C_PIO_PD9) /* ETM ARM9 pipeline status 0*/
/*****************************************************************************
SOFTWARE API DEFINITION FOR Power Management Controler
*****************************************************************************
*** Register offset in AT91S_PMC structure ***/
#define AT91C_PIOC_PeripheralA (0xFFFF0000) /* (BFC) PC16-PC31 set as Peripheral A*/
#define AT91C_SDRMC_CR_SET (0x2188c155)
#define AT91C_PIOA_DBGU_SET (0xC0000000) /* (BFC) PA30/PA31 set as DBGU*/
#define AT91C_DBGU_MAINCLK 60000000 /* 60 MHz*/
#define AT91C_DBGU_BAUDRATE 115200 /*baudrate to be programmed*/
/* Integrator 940T core module registers. */
#define INTEGRATOR_HDR_ID_OFFSET 0x00
#define INTEGRATOR_HDR_PROC_OFFSET 0x04
#define INTEGRATOR_HDR_OSC_OFFSET 0x08
#define INTEGRATOR_HDR_CTRL_OFFSET 0x0C
#define INTEGRATOR_HDR_STAT_OFFSET 0x10
#define INTEGRATOR_HDR_LOCK_OFFSET 0x14
#define INTEGRATOR_HDR_SDRAM_OFFSET 0x20
#define INTEGRATOR_HDR_INIT_OFFSET 0x24
#define INTEGRATOR_HDR_IC_OFFSET 0x40
#define INTEGRATOR_HDR_SPDBASE_OFFSET 0x100
#define INTEGRATOR_HDR_SPDTOP_OFFSET 0x200
#define INTEGRATOR_HDR_CTRL_FASTBUS 0x40
#define INTEGRATOR_HDR_BASE 0x10000000
#define INTEGRATOR_HDR_ID (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET)
#define INTEGRATOR_HDR_PROC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET)
#define INTEGRATOR_HDR_OSC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET)
#define INTEGRATOR_HDR_CTRL (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET)
#define INTEGRATOR_HDR_STAT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET)
#define INTEGRATOR_HDR_LOCK (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET)
#define INTEGRATOR_HDR_SDRAM (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET)
#define INTEGRATOR_HDR_INIT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET)
#define INTEGRATOR_HDR_IC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET)
#define INTEGRATOR_HDR_SPDBASE \
(INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET)
#define INTEGRATOR_HDR_SPDTOP \
(INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET)
#define INTEGRATOR_HDR_OSC_CORE_10MHz (0x102)
#define INTEGRATOR_HDR_OSC_CORE_15MHz (0x107)
#define INTEGRATOR_HDR_OSC_CORE_20MHz (0x10C)
#define INTEGRATOR_HDR_OSC_CORE_25MHz (0x111)
#define INTEGRATOR_HDR_OSC_CORE_30MHz (0x116)
#define INTEGRATOR_HDR_OSC_CORE_35MHz (0x11B)
#define INTEGRATOR_HDR_OSC_CORE_40MHz (0x120)
#define INTEGRATOR_HDR_OSC_CORE_45MHz (0x125)
#define INTEGRATOR_HDR_OSC_CORE_50MHz (0x12A)
#define INTEGRATOR_HDR_OSC_CORE_55MHz (0x12F)
#define INTEGRATOR_HDR_OSC_CORE_60MHz (0x134)
#define INTEGRATOR_HDR_OSC_CORE_65MHz (0x139)
#define INTEGRATOR_HDR_OSC_CORE_70MHz (0x13E)
#define INTEGRATOR_HDR_OSC_CORE_75MHz (0x143)
#define INTEGRATOR_HDR_OSC_CORE_80MHz (0x148)
#define INTEGRATOR_HDR_OSC_CORE_85MHz (0x14D)
#define INTEGRATOR_HDR_OSC_CORE_90MHz (0x152)
#define INTEGRATOR_HDR_OSC_CORE_95MHz (0x157)
#define INTEGRATOR_HDR_OSC_CORE_100MHz (0x15C)
#define INTEGRATOR_HDR_OSC_CORE_105MHz (0x161)
#define INTEGRATOR_HDR_OSC_CORE_110MHz (0x166)
#define INTEGRATOR_HDR_OSC_CORE_115MHz (0x16B)
#define INTEGRATOR_HDR_OSC_CORE_120MHz (0x170)
#define INTEGRATOR_HDR_OSC_CORE_125MHz (0x175)
#define INTEGRATOR_HDR_OSC_CORE_130MHz (0x17A)
#define INTEGRATOR_HDR_OSC_CORE_135MHz (0x17F)
#define INTEGRATOR_HDR_OSC_CORE_140MHz (0x184)
#define INTEGRATOR_HDR_OSC_CORE_145MHz (0x189)
#define INTEGRATOR_HDR_OSC_CORE_150MHz (0x18E)
#define INTEGRATOR_HDR_OSC_CORE_155MHz (0x193)
#define INTEGRATOR_HDR_OSC_CORE_160MHz (0x198)
#define INTEGRATOR_HDR_OSC_CORE_MASK (0x7FF)
#define INTEGRATOR_HDR_OSC_MEM_10MHz (0x10C000)
#define INTEGRATOR_HDR_OSC_MEM_15MHz (0x116000)
#define INTEGRATOR_HDR_OSC_MEM_20MHz (0x120000)
#define INTEGRATOR_HDR_OSC_MEM_25MHz (0x12A000)
#define INTEGRATOR_HDR_OSC_MEM_30MHz (0x134000)
#define INTEGRATOR_HDR_OSC_MEM_33MHz (0x13A000)
#define INTEGRATOR_HDR_OSC_MEM_40MHz (0x148000)
#define INTEGRATOR_HDR_OSC_MEM_50MHz (0x15C000)
#define INTEGRATOR_HDR_OSC_MEM_60MHz (0x170000)
#define INTEGRATOR_HDR_OSC_MEM_66MHz (0x17C000)
#define INTEGRATOR_HDR_OSC_MEM_MASK (0x7FF000)
/*
* Values we use for core and memory clocks on different header cards. Later
* versions of cards and/or upgraded FPGAs on the boards may enable the cards
* to run at faster speeds.
*
* These are:
*
* Processor Core Memory Bus System Bus PCI Bus
* ========= ==== ========== ========== =======
* Unknown 40MHz 20MHz 20MHz 33MHz
* ARM720T 50MHz 40MHz 20MHz 33MHz
* ARM740T 50MHz 40MHz 20MHz 33MHz
* ARM920T 140MHz 25MHz 20MHz 33MHz
* ARM940T 100MHz 25MHz 20MHz 33MHz
* ARM946ES 100MHz 25MHz 20MHz 33MHz
* ARM966ES 120MHz 40MHz 20MHz 33MHz
*
* NOTE
* ====
* The memory bus frequency of 25 MHz for ARM 9 cores is a very
* conservative figure. Depending on silicon manufacturer and version, it may
* be possible to select a higher frequency by experimentation.
*/
#define INTEGRATOR_HDR_OSC_DFLT_VAL \
(INTEGRATOR_HDR_OSC_CORE_40MHz | INTEGRATOR_HDR_OSC_MEM_20MHz)
#define INTEGRATOR_HDR_OSC_720T_VAL \
(INTEGRATOR_HDR_OSC_CORE_50MHz | INTEGRATOR_HDR_OSC_MEM_40MHz)
#define INTEGRATOR_HDR_OSC_740T_VAL \
(INTEGRATOR_HDR_OSC_CORE_50MHz | INTEGRATOR_HDR_OSC_MEM_25MHz)
#define INTEGRATOR_HDR_OSC_920T_VAL \
(INTEGRATOR_HDR_OSC_CORE_140MHz | INTEGRATOR_HDR_OSC_MEM_25MHz)
#define INTEGRATOR_HDR_OSC_940T_VAL \
(INTEGRATOR_HDR_OSC_CORE_100MHz | INTEGRATOR_HDR_OSC_MEM_25MHz)
#define INTEGRATOR_HDR_OSC_946ES_VAL \
(INTEGRATOR_HDR_OSC_CORE_80MHz | INTEGRATOR_HDR_OSC_MEM_25MHz)
#define INTEGRATOR_HDR_OSC_966ES_VAL INTEGRATOR_HDR_OSC_CORE_120MHz
#define INTEGRATOR_HDR_REMAP 0x4
#define INTEGRATOR_HDR_SDRAM_SPD_OK 0x20
#define INTEGRATOR_HDR_PLLBYPASS_ON 0x3
#define INTEGRATOR_HDR_HCLKDIV_3 0x20
#define INTEGRATOR_HDR_CLKRATIO_2 0x100
#define INTEGRATOR_HDR_TCRAM_ENABLE 0x10000
#define INTEGRATOR_HDR_TCRAM_EMULATE 0x20000
/* Integrator EBI register definitions. */
#define AT91C_EBI_DBPUC (0x1 << 0) /* (EBI) Data Bus Pull-Up Configuration*/
#define AT91C_EBI_EBSEN (0x1 << 1) /* (EBI) Bus Sharing Enable*/
#define AT91C_SMC2_TDF 0x200 /*Data Float Time*/
#define AT91C_SMC2_NWS 0x4 /*Number of Wait States*/
#define AT91C_SMC2_WSEN 0x80 /* Wait State Enable*/
#define AT91C_SMC2_BAT 0x1000 /*Byte Access Type*/
#define AT91C_SMC2_DBW_16 0x2000 /* 16-bit */
#define AT91C_SMC2_RWSETUP
/*#define INTEGRATOR_EBI_BASE 0x12000000*/
#define INTEGRATOR_MC_BASE 0xffffff00
#define INTEGRATOR_EBI_BASE 0xffffff60
/*#define INTEGRATOR_EBI_CSR0_OFFSET 0x00*/
#define INTEGRATOR_EBI_CSR0_OFFSET 0x10 /*0x10-0x2c SMC controller, 0x10-SMC_CSR0*/
/*#define INTEGRATOR_EBI_CSR1_OFFSET 0x04*/
#define INTEGRATOR_EBI_CSR1_OFFSET 0x30 /*0x30-0x5c SDRAM controller*/
/*#define INTEGRATOR_EBI_CSR2_OFFSET 0x08 */
#define INTEGRATOR_EBI_CSR2_OFFSET 0x18 /*0x18-SMC_CSR2*/
/*#define INTEGRATOR_EBI_CSR3_OFFSET 0x0C*/
#define INTEGRATOR_EBI_CSR3_OFFSET 0x1C /*0x1c-SMC_CSR3*/
#define INTEGRATOR_EBI_LOCK_OFFSET 0x20
#define INTEGRATOR_EBI_CSR0 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET)
#define INTEGRATOR_EBI_CSR1 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
#define INTEGRATOR_EBI_CSR2 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET)
#define INTEGRATOR_EBI_CSR3 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET)
#define INTEGRATOR_EBI_LOCK (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
#define INTEGRATOR_EBI_8_BIT 0x00
#define INTEGRATOR_EBI_16_BIT 0x01
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -