integrator.h

ATMEL920T的BSP及ETH等已经设备驱动程序

/* integrator.h - ARM Integrator header file */

/* Copyright 1999-2002 Wind River Systems, Inc. */
/* Copyright 1999-2000 ARM Limited */

/*
modification history
--------------------
01q,16jul02,m_h  C++ protection
01p,24apr02,to   fixed PCI_MEM_ADRS. defined macros for PCI to CPU offset.
01o,10jan02,m_h  fix NVRAM
01n,31oct01,rec  use generic driver for amba timer
01m,09oct01,jpd  added 946ES speed definitions.
01l,09oct01,m_h  PCI requires larger memory size for windML
01k,22jun01,m_h  WindML support
01j,04jun01,rec  memory clock rate changes for 740t
01i,21feb01,h_k  added support for ARM966ES and ARM966ES_T.
01h,24nov00,jpd  added header card SSRAM size and Ethernet definitions;
		 added header card speed definitions; moved NVRAM Flash for more
		 ROMmed code space; reworked PCI memory and I/O space
		 allocations;
01g,15sep00,rec  add definition for INTEGRATOR_MAX_END_DEVS
01f,14jun00,pr   added EBI_LOCK definitions.
01e,18feb00,jpd  moved FOOTER to config.h.
01d,07feb00,jpd  added Flash definitions.
01c,13jan00,pr	 added support for Integrator 740T.
01b,07dec99,pr	 add support for PCI.
01a,08nov99,ajb  modified from pid7t template.
*/

/*
This file contains I/O address and related constants for the ARM
Integrator board.
*/

#ifndef	INCintegratorh
#define	INCintegratorh

#ifdef __cplusplus
extern "C" {
#endif

#define TARGET_INTEGRATOR

/* Flash definitions */

#define FLASH_BASE		0x10000000	/* Base address of Flash part */
/*#define FLASH_BASE		0x24000000	*//* Base address of Flash part */
#define FLASH_BLOCK_NUM		70		/* 64 kB block used as NVRAM */
/*#define FLASH_BLOCK_NUM		254		*//* 128 kB block used as NVRAM */
/*#define FLASH_ADRS		(FLASH_BASE + (FLASH_BLOCK_NUM * 0x20000))*/
#define FLASH_ADRS		FLASH_BASE		/*   */
/*#define INTEGRATOR_FLASH_SIZE 	0x02000000 	*//* Total Flash available. */
#define INTEGRATOR_FLASH_SIZE 	0x00400000 	/* 4Mbytes for AT49BV322A Total. */
#define FLASH_SIZE_WRITEABLE INTEGRATOR_FLASH_SIZE-SZ_64K /*64Kbytes reserved as  NVRAM*/
#define NV_RAM_ADRS	(FLASH_BASE + 0x3F0000)	/* for AT49BV322A*/
#define NV_RAM_CONFIG_ADRS	(FLASH_BASE + 0x3d0000)	/* for AT49BV322A*/
#define NV_RAM_OS_ADRS			(FLASH_BASE + 0x100000)	/* for AT49BV322A*/
#define FLASH_SECTOR_SIZE	SZ_64K		/* for AT49BV322A*/
#define FLASH_WIDTH		2	  	/*  16-bit wide parts */
#define FLASH_CHIP_WIDTH        2
#define FLASH_WIDTH_SPECIAL_2			/* see flash28.h */
#define SYS_FLASH_WRITE				/* use enable/disable routines*/

/*
 * It is not necessary to define SYS_FLASH_TYPE as FLASH_28F320 as
 * auto-identification correctly identifies the Flash part.
 */


/* Integrator memory map */

#define INTEGRATOR_PERIPHERAL_BASE	0x10000000
#define INTEGRATOR_PERIPHERAL_SIZE	0x10000000

#define INTEGRATOR_BOOT_ROM_LO          0x00000000
#define INTEGRATOR_BOOT_ROM_HI          0x20000000
#define INTEGRATOR_BOOT_ROM_BASE        INTEGRATOR_BOOT_ROM_HI
#define INTEGRATOR_BOOT_ROM_SIZE	0x00080000

/*
 *  New Core Modules have different amounts of SSRAM,
 *  the amount of SSRAM fitted can be found in HDR_STAT.
 *
 *  The symbol INTEGRATOR_SSRAM_SIZE is kept, however this
 *  now refers to the minimum amount of SSRAM fitted on any
 *  core module.
 *
 *  New Core Modules also alias the SSRAM.
 */

#define INTEGRATOR_SSRAM_BASE           0x00000000
#define INTEGRATOR_SSRAM_ALIAS_BASE     0x10800000
#define INTEGRATOR_SSRAM_SIZE           SZ_256K

#if defined(CPU_920T)  || defined(CPU_920T_T)  || \
    defined(CPU_946ES) || defined(CPU_946ES_T) || \
    defined(CPU_966ES) || defined(CPU_966ES_T)
/*#define INTEGRATOR_HDR_SSRAM_SIZE	SZ_1M*/
#define INTEGRATOR_HDR_SSRAM_SIZE	SZ_256K
#else
#define INTEGRATOR_HDR_SSRAM_SIZE	SZ_256K
#endif

#define INTEGRATOR_MBRD_SSRAM_BASE      0x28000000
#define INTEGRATOR_MBRD_SSRAM_SIZE      SZ_512K

/*  SDRAM is a DIMM therefore the size is not known. */

#define INTEGRATOR_SDRAM_BASE           0x00040000

#define INTEGRATOR_SDRAM_ALIAS_BASE     0x80000000
#define INTEGRATOR_HDR0_SDRAM_BASE      0x80000000
#define INTEGRATOR_HDR1_SDRAM_BASE      0x90000000
#define INTEGRATOR_HDR2_SDRAM_BASE      0xA0000000
#define INTEGRATOR_HDR3_SDRAM_BASE      0xB0000000

/* RAM base in reset memory map */

#define INTEGRATOR_RESET_RAM_BASE	0x28000000

/* UART 16C554 base */
#define INTEGRATOR_UART_16C554_BASE	0x30000000

/* PCI Base area */

#define INTEGRATOR_PCI_BASE		0x40000000
#define INTEGRATOR_PCI_SIZE		0x3FFFFFFF

#define BUS		BUS_TYPE_PCI


/* Signals generated from Integrator clock generator. */

#define INTEGRATOR_SYSCLK   20000000		/* System bus clock */
#define INTEGRATOR_P_CLK    33000000		/* PCI clock */
/*#define INTEGRATOR_UARTCLK  14745600		*//* UART clock */
#define INTEGRATOR_UARTCLK  AT91C_DBGU_MAINCLK	/* UART clock */


#define INTEGRATOR_CLK24MHZ 24000000		/* KMI/Timer clock */


#define AT91C_PLLAR 			(0x2026BE04)	/* 179,712000 MHz for PCK */
#define AT91C_PLLBR 				0x10483E0E	/* 48,054857 MHz (divider by 2 for USB)*/
#define AT91C_MCKR  				0x00000202	/* PCK/3 = MCK Master Clock = 59,904000MHz with PLLA selected */
#define AT91C_SLOWCLOCK		32768		/* In Hz*/
#define AT91C_PMC_SR              	(0x68) 			/* (PMC) Status Register offset*/
#define AT91C_PMC_MCKR              	(0x30) 			/* (PMC) Master CLock Register offset*/
#define AT91C_PMC_LOCKA   		(0x1 <<  1) 	/* (PMC) PLL A Status/Enable/Disable/Mask*/
#define AT91C_PMC_LOCKB           	(0x1 <<  2)   /* (PMC) PLL B Status/Enable/Disable/Mask*/
#define AT91C_PMC_MCKRDY          (0x1 <<  3)   /* (PMC) MCK_RDY Status/Enable/Disable/Mask*/
#define AT91C_CKGR_MOSCEN         (0x1 <<  0)	/* */
#define AT91C_CKGR_OSCOUNT        (0xFF <<  8) /* */

/* BASE ADDRESS DEFINITIONS FOR AT91RM9200. */
#define AT91C_BASE_SYS            (0xFFFFF000) /* (SYS) Base Address	*/
#define AT91C_BASE_MC             (0xFFFFFF00) /* (MC) Base Address*/
#define AT91C_BASE_RTC            (0xFFFFFE00) /* (RTC) Base Address*/
#define AT91C_BASE_ST             (0xFFFFFD00) /* (ST) Base Address*/
#define AT91C_BASE_PMC            (0xFFFFFC00) /* (PMC) Base Address*/
#define AT91C_BASE_CKGR           (0xFFFFFC20) /* (CKGR) Base Address*/
#define AT91C_BASE_PIOD           (0xFFFFFA00) /* (PIOD) Base Address*/
#define AT91C_BASE_PIOC           (0xFFFFF800) /* (PIOC) Base Address*/
#define AT91C_BASE_PIOB           (0xFFFFF600) /* (PIOB) Base Address*/
#define AT91C_BASE_PIOA           (0xFFFFF400) /* (PIOA) Base Address*/
#define AT91C_BASE_DBGU           (0xFFFFF200) /* (DBGU) Base Address*/
#define AT91C_BASE_PDC_DBGU       (0xFFFFF300) /* (PDC_DBGU) Base Address*/
#define AT91C_BASE_AIC            (0xFFFFF000) /* (AIC) Base Address*/
#define AT91C_BASE_PDC_SPI        (0xFFFE0100) /* (PDC_SPI) Base Address*/
#define AT91C_BASE_SPI            (0xFFFE0000) /* (SPI) Base Address*/
#define AT91C_BASE_PDC_SSC2       (0xFFFD8100) /* (PDC_SSC2) Base Address*/
#define AT91C_BASE_SSC2           (0xFFFD8000) /* (SSC2) Base Address*/
#define AT91C_BASE_PDC_SSC1       (0xFFFD4100) /* (PDC_SSC1) Base Address*/
#define AT91C_BASE_SSC1           (0xFFFD4000) /* (SSC1) Base Address*/
#define AT91C_BASE_PDC_SSC0       (0xFFFD0100) /* (PDC_SSC0) Base Address*/
#define AT91C_BASE_SSC0           (0xFFFD0000) /* (SSC0) Base Address*/
#define AT91C_BASE_PDC_US3        (0xFFFCC100) /* (PDC_US3) Base Address*/
#define AT91C_BASE_US3            (0xFFFCC000) /* (US3) Base Address*/
#define AT91C_BASE_PDC_US2        (0xFFFC8100) /* (PDC_US2) Base Address*/
#define AT91C_BASE_US2            (0xFFFC8000) /* (US2) Base Address*/
#define AT91C_BASE_PDC_US1        (0xFFFC4100) /* (PDC_US1) Base Address*/
#define AT91C_BASE_US1            (0xFFFC4000) /* (US1) Base Address*/
#define AT91C_BASE_PDC_US0        (0xFFFC0100) /* (PDC_US0) Base Address*/
#define AT91C_BASE_US0            (0xFFFC0000) /* (US0) Base Address*/
#define AT91C_BASE_TWI            (0xFFFB8000) /* (TWI) Base Address*/
#define AT91C_BASE_PDC_MCI        (0xFFFB4100) /* (PDC_MCI) Base Address*/
#define AT91C_BASE_MCI            (0xFFFB4000) /* (MCI) Base Address*/
#define AT91C_BASE_UDP            (0xFFFB0000) /* (UDP) Base Address*/
#define AT91C_BASE_TC5            (0xFFFA4080) /* (TC5) Base Address*/
#define AT91C_BASE_TC4            (0xFFFA4040) /* (TC4) Base Address*/
#define AT91C_BASE_TC3            (0xFFFA4000) /* (TC3) Base Address*/
#define AT91C_BASE_TCB1           (0xFFFA4080) /* (TCB1) Base Address*/
#define AT91C_BASE_TC2            (0xFFFA0080) /* (TC2) Base Address*/
#define AT91C_BASE_TC1            (0xFFFA0040) /* (TC1) Base Address*/
#define AT91C_BASE_TC0            (0xFFFA0000) /* (TC0) Base Address*/
#define AT91C_BASE_TCB0           (0xFFFA0000) /* (TCB0) Base Address*/
#define AT91C_BASE_UHP            (0x00300000) /* (UHP) Base Address*/
#define AT91C_BASE_EMAC           (0xFFFBC000) /* (EMAC) Base Address*/
#define AT91C_BASE_EBI            (0xFFFFFF60) /* (EBI) Base Address*/
#define AT91C_BASE_SMC2           (0xFFFFFF70) /* (SMC2) Base Address*/
#define AT91C_BASE_SDRC           (0xFFFFFF90) /* (SDRC) Base Address*/
#define AT91C_BASE_BFC            (0xFFFFFFC0) /* (BFC) Base Address*/


/*  Register offset in AT91S_PIO structure  */
#define PIO_PER         ( 0) /*  PIO Enable Register*/
#define PIO_PDR         ( 4) /*  PIO Disable Register*/
#define PIO_PSR         ( 8) /*  PIO Status Register*/
#define PIO_OER         (16) /*  Output Enable Register*/
#define PIO_ODR         (20) /*  Output Disable Registerr*/
#define PIO_OSR         (24) /*  Output Status Register*/
#define PIO_IFER        (32) /*  Input Filter Enable Register*/
#define PIO_IFDR        (36) /*  Input Filter Disable Register*/
#define PIO_IFSR        (40) /*  Input Filter Status Register*/
#define PIO_SODR        (48) /*  Set Output Data Register*/
#define PIO_CODR        (52) /*  Clear Output Data Register*/
#define PIO_ODSR        (56)/*  Output Data Status Register*/
#define PIO_PDSR        (60) /*  Pin Data Status Register*/
#define PIO_IER         (64) /*  Interrupt Enable Register*/
#define PIO_IDR         (68) /*  Interrupt Disable Register*/
#define PIO_IMR         (72) /*  Interrupt Mask Register*/
#define PIO_ISR         (76) /*  Interrupt Status Register*/
#define PIO_MDER        (80) /*  Multi-driver Enable Register*/
#define PIO_MDDR        (84) /*  Multi-driver Disable Register*/
#define PIO_MDSR        (88) /*  Multi-driver Status Register*/
#define PIO_PPUDR       (96) /*  Pull-up Disable Register*/
#define PIO_PPUER       (100) /*  Pull-up Enable Register*/
#define PIO_PPUSR       (104) /*  Pad Pull-up Status Register*/
#define PIO_ASR         (112) /*  Select A Register*/
#define PIO_BSR         (116) /*  Select B Register*/
#define PIO_ABSR        (120) /*  AB Select Status Register*/
#define PIO_OWER        (160) /*  Output Write Enable Register*/
#define PIO_OWDR        (164) /*  Output Write Disable Register*/
#define PIO_OWSR        (168) /*  Output Write Status Register*/

/*  Register offset for SMC */
#define SMC_CSR0	(0x0)	/*  SMC Chip Select Register 0 */
#define SMC_CSR1	(0x4)	/*  SMC Chip Select Register 1 */
#define SMC_CSR2	(0x8)	/*  SMC Chip Select Register 2 */
#define SMC_CSR3	(0xc)	/*  SMC Chip Select Register 3 */
#define SMC_CSR4	(0x10)	/*  SMC Chip Select Register 4 */
#define SMC_CSR5	(0x14)	/*  SMC Chip Select Register 5 */
#define SMC_CSR6	(0x18)	/*  SMC Chip Select Register 6 */
#define SMC_CSR7	(0x1c)	/*  SMC Chip Select Register 7 */

/*  Register offset for EBI */
#define EBI_CSA		(0x0)	/*  Chip Select Assignment Register*/