📄 rominit.s
字号:
STR r2, [r1, #INTEGRATOR_SC_LOCK_OFFSET]
*/
/* Initialize static memory. */
/* CS0 - ROM (Boot Flash) */ /* init Flash */
MOV r1, #INTEGRATOR_MC_BASE
MOV r2,#0
STR r2, [r1, #0x10]
STR r2, [r1, #0x50]
STR r2, [r1, #0x54] /*Memory controller protection unit disable*/
STR r2, [r1, #0x4] /* read only */
STR r2, [r1, #0x8] /* read only */
MOV r1, #INTEGRATOR_EBI_BASE
LDR r2, [r1, #0x0]
AND r2, r2, #0xFFFFFFFE
STR r2, [r1, #0x0]
MOV r2, #AT91C_EBI_DBPUC & 0x00
ORR r2, r2, #AT91C_EBI_EBSEN & 0x00
STR r2, [r1, #0x4] /* [D15:0] Data Bus bits are internally pulled-up to the VDDIOM power supply. */
MOV r2, #AT91C_SMC2_DBW_16 | AT91C_SMC2_BAT | AT91C_SMC2_TDF
ORR r2, r2, # AT91C_SMC2_WSEN | AT91C_SMC2_NWS
STR r2, [r1, #INTEGRATOR_EBI_CSR0_OFFSET] /* Set SMC_CSR0 Register*/
/* init Clock */
/* Check if Input & Output Frequencies are in the correct range*/
/* Check Input & Output Frequencies end */
/* Setting PLLA and Divider A */
LDR r1, =AT91C_BASE_CKGR
LDR r2, =AT91C_PLLAR
STR r2, [r1, #0x8]
LDR r1, =AT91C_BASE_PMC
MOV r3,#0x64
delay_plla:
LDR r2, [r1, #AT91C_PMC_SR]
AND r2, r2, #AT91C_PMC_LOCKA
CMP r2, #0x0
BNE delay_plla_end /* Wait for PLLA stabilization LOCKA bit in PMC_SR*/
SUBS r3, r3, #1
CMP r3, #0x0
BNE delay_plla
delay_plla_end:
/* Setting PLLB and Divider B */
LDR r1, =AT91C_BASE_CKGR
LDR r2, =AT91C_PLLBR
STR r2, [r1, #0xc]
LDR r1, =AT91C_BASE_PMC
MOV r3,#0x64
delay_pllb:
LDR r2, [r1, #AT91C_PMC_SR]
AND r2, r2, #AT91C_PMC_LOCKB
CMP r2, #0x0
BNE delay_pllb_end /* Wait for PLLB stabilization LOCKB bit in PMC_SR*/
SUBS r3, r3, #1
CMP r3, #0x0
BNE delay_pllb
delay_pllb_end:
/* Selection of Master Clock MCK (and Processor Clock PCK) */
LDR r1, =AT91C_BASE_PMC
LDR r2, =AT91C_MCKR
STR r2, [r1, #AT91C_PMC_MCKR]
LDR r1, =AT91C_BASE_PMC
MOV r3,#0x64
delay_mainf:
LDR r2, [r1, #AT91C_PMC_SR]
AND r2, r2, #AT91C_PMC_MCKRDY
CMP r2, #0x0
BNE delay_mainf_end /* Wait until the master clock is established*/
SUBS r3, r3, #1
CMP r3, #0x0
BNE delay_mainf
delay_mainf_end:
/* SDRAM Initialisation */
LDR r1, =AT91C_BASE_PIOC
LDR r2, =AT91C_PIOC_PeripheralA
STR r2, [r1, #PIO_ASR]
STR r2, [r1, #PIO_PDR] /* Configure PIOC as peripheral (D16/D31) */
MOV r1, #AT91C_BASE_EBI
LDR r2, [r1, #0x0]
ORR r2, r2, #0x2
STR r2, [r1, #0x0] /* Setup MEMC to support CS1=SDRAM*/
MOV r2, #0x0
STR r2, [r1, #0x4] /* Data Bus bits are internally pulled-up to the VDDIOM power supply.*/
/*1. A minimum pause of 200us is provided to precede any signal toggle */
MOV r1, #AT91C_BASE_SDRC
LDR r2, =AT91C_SDRMC_CR_SET
STR r2, [r1, #0x8]
/* 2. A Precharge All command is issued to the SDRAM*/
MOV r2, #0x2
STR r2, [r1, #0x0] /* attention !!!*/
MOV r3, #0x20000000
MOV r2, #0x0
STR r2, [r3, #0x0]
/* 3. Eight Auto-refresh are provided */
MOV r2, #0x4
STR r2, [r1, #0x0] /* attention !!!*/
MOV r2, #0x0
STR r2, [r3, #0x0]
STR r2, [r3, #0x0]
STR r2, [r3, #0x0]
STR r2, [r3, #0x0]
STR r2, [r3, #0x0]
STR r2, [r3, #0x0]
STR r2, [r3, #0x0]
STR r2, [r3, #0x0]
/* 4. A mode register cycle is issued to program the SDRAM parameters */
MOV r2, #0x3
STR r2, [r1, #0x0]
MOV r2, #0x0
STR r2, [r3, #0x80]
/* 5. Write refresh rate into SDRAMC refresh timer COUNT register*/
MOV r2, #0xfff & 0x2E0
STR r2, [r1, #0x4]
MOV r2, #0x0
STR r2, [r3, #0x0]
/* 6. A Normal Mode Command is provided, 3 clocks after tMRD is set*/
MOV r2, #0x0
STR r2, [r1, #0x0]
MOV r2, #0x0
STR r2, [r3, #0x80]
/* DBGU port Initialisation*/
/* Open PIOA for DBGU */
LDR r1, =AT91C_BASE_PIOA
LDR r2, =AT91C_PIOA_DBGU_SET
STR r2, [r1, #PIO_ASR]
STR r2, [r1, #PIO_PDR] /* Configure PIOA as DBGU (PA30/PA31) */
/* Configure DBGU*/
LDR r1, =AT91C_BASE_DBGU
MVN r2, #0 /* 0xFFFFFFFF */
STR r2, [r1, #0xc] /* Disable interrupts */
MOV r2, #0xac
STR r2, [r1, #0x0] /* Reset receiver and transmitter */
LDR r2, =AT91C_DBGU_BAUDRATE
MOV r1, #0x10
MUL r3, r1, r2
MOV r2, #0x0
LDR r1, =AT91C_DBGU_MAINCLK
loop_dbgu1:
CMP r1, r3
BLS loop_dbgu1_end
SUB r1, r1, r3
ADD r2, r2, #0x1
B loop_dbgu1
loop_dbgu1_end:
LDR r3, =AT91C_DBGU_BAUDRATE
MOV r4, #0x8
MUL r3, r4, r3
CMP r1, r3
ADDHI r2, r2, #0x1 /* Caluculate baud_value according to the main clock and the baud rate*/
LDR r1, =AT91C_BASE_DBGU
STR r2, [r1, #0x20] /* Define the baud rate divisor register*/
MOV r2, #0x0
STR r2, [r1, #0x28] /* Write the Timeguard Register*/
LDR r1, =AT91C_BASE_DBGU
ADD r1, r1, #0x100 /* Change to PDC BASE Address*/
MOV r2, #(0x1 << 1)
STR r2, [r1, #0x20] /* Disable the RX PDC transfer requests*/
MOV r2, #(0x1 << 9)
STR r2, [r1, #0x20] /* Disable the TX PDC transfer requests*/
MOV r2, #0x0
STR r2, [r1, #0x18]
STR r2, [r1, #0x1c] /* Set the next transmit transfer descriptor*/
MOV r2, #0x0
STR r2, [r1, #0x10]
STR r2, [r1, #0x14] /* Set the next receive transfer descriptor */
MOV r2, #0x0
STR r2, [r1, #0x8]
STR r2, [r1, #0xc] /* Set the transmit transfer descriptor */
MOV r2, #0x0
STR r2, [r1, #0x0]
STR r2, [r1, #0x4] /* Set the receive transfer descriptor */
MOV r2, #(0x1 << 0)
STR r2, [r1, #0x20] /* Enable the RX PDC transfer requests*/
MOV r2, #(0x1 << 8)
STR r2, [r1, #0x20] /* Enable the TX PDC transfer requests*/
LDR r1, =AT91C_BASE_DBGU
MOV r2, #(0x4 << 9)
STR r2, [r1, #0x4] /* Define the USART mode Normal Mode/No parity */
MOV r2, #(0x1 << 6)
STR r2, [r1, #0x0] /* Enable sending characters*/
/* DBGU port Initialisation end*/
LDR r1, =AT91C_BASE_DBGU
MOV r4, #0x6 /* Output 6 'S' character */
loop_DBGU_test:
MOV r3, #0xF0000
LDR r2, [r1, #0x14]
AND r2, r2, #(0x1 << 1)
CMP r2, #0x0
BEQ loop_DBGU_test_end
MOV r2,#0x2e /* '.' character */
/* MOV r2,#0x53*/
STR r2, [r1, #0x1c]
loop_DBDU_delay:
SUB r3, r3, #0x1
CMP r3, #0x0
BNE loop_DBDU_delay
SUB r4, r4, #0x1
CMP r4, #0x0
BNE loop_DBGU_test
loop_DBGU_test_end:
B init_stack
/* CS1 - Flash (Application Flash) */
/*
MOV r2, #INTEGRATOR_EBI_32_BIT | INTEGRATOR_EBI_WS_3
STR r2, [r1, #INTEGRATOR_EBI_CSR1_OFFSET]
*/
/* CS2 - SSRAM (Not on Rev A Boards) */
/*
MOV r2, #INTEGRATOR_EBI_32_BIT | INTEGRATOR_EBI_WRITE_ENABLE | \
INTEGRATOR_EBI_SYNC | INTEGRATOR_EBI_WS_2
STR r2, [r1, #INTEGRATOR_EBI_CSR2_OFFSET]
*/
/* CS3 - Unused (Set up for debug) */
/*
MOV r2, #INTEGRATOR_EBI_8_BIT | INTEGRATOR_EBI_WRITE_ENABLE
STR r2, [r1, #INTEGRATOR_EBI_CSR3_OFFSET]
*/
/*
* Initialize external target memory.
* Copied (with modifications for GNU) from uHAL.
*
* Size SDRAM (see CM940T User Guide, ARM DUI0125A - s.4.3.8, p.4-16)
*
* Check to see if the SPD data has been loaded. If the load has
* not completed we will loop upto 64K times before giving up.
*/
LDR r1, =INTEGRATOR_HDR_SDRAM /* Load address of HDR_SDRAM */
MOV r2, #0x10000 /* Load count */
sdram1:
LDR r3, [r1] /* Load contents of HDR_SDRAM */
/* Check to see if SPD data is loaded */
TST r3, #INTEGRATOR_HDR_SDRAM_SPD_OK
BNE sdram2
SUBS r2, r2, #1 /* Decrement the count */
B sdram5
sdram2:
/* Load address of the base of SPD data */
LDR r1, =INTEGRATOR_HDR_SPDBASE
MOV r3, #0
/* Calculate the memory size from the SPD data. */
LDRB r2, [r1, #31] /* Get Module Bank Density */
MOV r2, r2, LSL #2 /* Multiply by 4 */
LDRB r3, [r1, #5] /* Get Number of Banks */
MULS r2, r3, r2 /* Multiply to to get size in MBytes */
BEQ sdram5 /* If zero then something's gone wrong*/
/* The maximum SDRAM DIMM supported is 256 Mbytes */
CMP r2, #256
BGT sdram5
/*
* We need to convert the size in MBytes to the value the value
* to write to the MEMSIZE field of HDR_SDRAM. The formula to do
* this is as follows -
*
* MEMSIZE = LOG2(SizeInMB) - 4
*
* All the sizes that are supported are powers of 2 so a simple
* algorithm to find LOG2 of number is to count the number of trailing
* zeros.
*/
MOV r1, #0 /* Initialise the counter */
sdram4:
TST r2, #1 /* Is the bottom bit set of the size varible */
MOVEQ r2, r2, LSR #1 /* If not set then divide by 2 */
ADDEQ r1, r1, #1 /* If not set then increment the counter */
BEQ sdram4 /* If not set then loop */
CMP r2, #1 /* $w2 should now contain 1 */
BNE sdram5 /* If it doesn't then something has gone wrong*/
/* Load base address of header registers */
LDR r2, =INTEGRATOR_HDR_BASE
/* Load contents of HDR_SDRAM */
LDR r3, [r2, #INTEGRATOR_HDR_SDRAM_OFFSET]
AND r3, r3, #3 /* Clear the everything except CASLAT */
SUBS r1, r1, #4 /* Subtract 4 from the number of trailing bits*/
BMI sdram5 /* If negative then something has gone wrong */
ORR r3, r3, r1, LSL #2 /* Merge it into contents of HDR_SDRAM*/
LDRB r1, [r2, #(INTEGRATOR_HDR_SPDBASE_OFFSET + 3)] /* No. of Rows */
AND r1, r1, #0xF /* Only want bottom 4 bits */
ORR r3, r3, r1, LSL #8 /* Merge into HDR_SDRAM */
LDRB r1, [r2, #(INTEGRATOR_HDR_SPDBASE_OFFSET + 4)] /* Num Columns */
AND r1, r1, #0xF /* Only want bottom 4 bits */
ORR r3, r3, r1, LSL #12 /* Merge into HDR_SDRAM */
LDRB r1, [r2, #(INTEGRATOR_HDR_SPDBASE_OFFSET + 5)] /* No. of Banks*/
AND r1, r1, #0xF /* Only want bottom 4 bits */
ORR r3, r3, r1, LSL #16 /* Merge into HDR_SDRAM */
/* Write back to HDR_SDRAM */
STR r3, [r2, #INTEGRATOR_HDR_SDRAM_OFFSET]
/*
* Now calculate the size of memory in bytes, this is done by
* shifting 1 by MEMSIZE + 24. The magic number 24 is the 4 we
* subtracted earlier plus 20 to get the value is bytes (2^20
* being 1 Mbyte).
*/
MOV r1, r3, LSR #2 /* Need to extract MEMSIZE from the */
AND r1, r1, #0x7 /* value we wrote to HDR_SDRAM */
MOV r2, #1 /* Load 1 */
ADD r1, r1, #24 /* Add 24 to the MEMSIZE value */
MOV r1, r2, LSL r1 /* Shift 1 by (24 + MEMSIZE) */
B sdram6
sdram5:
MOV r1, #0 /* Could not find any good DRAM */
sdram6:
/* Load base address of header registers */
LDR r2, =INTEGRATOR_HDR_BASE
/* Load contents of HDR_STAT */
LDR r2, [r2, #INTEGRATOR_HDR_STAT_OFFSET]
/* Clear all but bits 23:16 to get SSRAM size */
ANDS r2, r2, #0xFF0000
/* If zero then this is a old header with 256K */
MOVEQ r2, #0x00040000
CMP r1, r2 /* Is there less SDRAM than the SSRAM */
MOVMI r1, r2 /* If so then return the size of the SSRAM */
/* r1 now contains memory size: store this in Memory_Size variable */
init_stack:
LDR r1, =LOCAL_MEM_SIZE
LDR r3, L$_memSize
STR r1, [r3]
MOV r3, r1 /* Need to return size in both these registers*/
/*
* End of DRAM initialisation.
*
* Initialize the stack pointer to just before where the
* uncompress code, copied from ROM to RAM, will run.
*/
LDR sp, L$_STACK_ADDR
MOV fp, #0 /* zero frame pointer */
/* jump to C entry point in ROM: routine - entry point + ROM base */
#if (ARM_THUMB)
LDR r12, L$_rStrtInRom
ORR r12, r12, #1 /* force Thumb state */
BX r12
#else
LDR pc, L$_rStrtInRom
#endif /* (ARM_THUMB) */
/******************************************************************************/
/*
* PC-relative-addressable pointers - LDR Rn,=sym is broken
* note "_" after "$" to stop preprocessor performing substitution
*/
.balign 4
L$_HiPosn:
.long ROM_TEXT_ADRS + HiPosn - FUNC(romInit)
L$_rStrtInRom:
.long ROM_TEXT_ADRS + FUNC(romStart) - FUNC(romInit)
L$_STACK_ADDR:
.long STACK_ADRS
L$_memSize:
.long VAR(integratorMemSize)
#if defined(CPU_940T) || defined (CPU_940T_T)
L$_sysCacheUncachedAdrs:
.long SYS_CACHE_UNCACHED_ADRS
#endif /* defined(CPU_940T, CPU_940T_T) */
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