shift.n

ze5开发板学习实验程序

// Netlist written August 18, 2004 8:12:07 AM CST
// By FastChip Version 3.0_Beta Build 040202-1214
// Netlist last modified August 18, 2004 8:12:07 AM CST
netlist
module SHIFT {
    input CLK;
    input CLKEn;
    input D [7:0];
    input load;
    input loadcp;
    net N000030;
    net N000050;
    net N000070;
    net N000090;
    net N000110;
    net N000130;
    net N000150;
    net N000170;
    net N000610;
    net N000922;
    net N00194;
    net N00198;
    net N00213;
    net N00220;
    net N00239;
    net N00248;
    net N00257;
    net N00261;
    net N00265;
    net N00274;
    net N00278;
    net N00283;
    net N00300;
    net N00304;
    net N00308;
    net N00317;
    net N00321;
    net N00325;
    net N00334;
    net N00338;
    net N00342;
    net N00352;
    net N007281;
    net N00745;
    output Q [7:0];
    input shiftin;
    output shiftout;
    and2 AND2_1 (.i0=shiftin, .i1=N00194, .o=N00248);
    and2 AND2_10 (.i0=Q[5], .i1=N00274, .o=N00278);
    and2 AND2_11 (.i0=Q[4], .i1=N00300, .o=N00304);
    and2 AND2_12 (.i0=Q[3], .i1=N00317, .o=N00321);
    and2 AND2_13 (.i0=Q[2], .i1=N00334, .o=N00338);
    and2 AND2_14 (.i0=Q[1], .i1=N000610, .o=N00352);
    and2 AND2_15 (.i0=D[7], .i1=load, .o=N00198);
    and2 AND2_16 (.i0=D[6], .i1=load, .o=N00220);
    and2 AND2_17 (.i0=D[5], .i1=load, .o=N00265);
    and2 AND2_18 (.i0=D[4], .i1=load, .o=N00283);
    and2 AND2_19 (.i0=D[3], .i1=load, .o=N00308);
    and2 AND2_20 (.i0=D[2], .i1=load, .o=N00325);
    and2 AND2_21 (.i0=D[1], .i1=load, .o=N00342);
    and2 AND2_22 (.i0=D[0], .i1=load, .o=N000922);
    and2 AND2_23 (.i0=CLK, .i1=CLKEn, .o=N007281);
    and2 AND2_8 (.i0=Q[7], .i1=N00213, .o=N00239);
    and2 AND2_9 (.i0=Q[6], .i1=N00257, .o=N00261);
    buf BUF_1 (.i=Q[0], .o=shiftout);
    dff DFFC_1 (.ck=N00745, .d=N000030, .en=vcc, .q=Q[7], .reset=gnd, :initv="0");
    dff DFFC_2 (.ck=N00745, .d=N000050, .en=vcc, .q=Q[6], .reset=gnd, :initv="0");
    dff DFFC_3 (.ck=N00745, .d=N000070, .en=vcc, .q=Q[5], .reset=gnd, :initv="0");
    dff DFFC_4 (.ck=N00745, .d=N000090, .en=vcc, .q=Q[4], .reset=gnd, :initv="0");
    dff DFFC_5 (.ck=N00745, .d=N000110, .en=vcc, .q=Q[3], .reset=gnd, :initv="0");
    dff DFFC_6 (.ck=N00745, .d=N000130, .en=vcc, .q=Q[2], .reset=gnd, :initv="0");
    dff DFFC_7 (.ck=N00745, .d=N000150, .en=vcc, .q=Q[1], .reset=gnd, :initv="0");
    dff DFFC_8 (.ck=N00745, .d=N000170, .en=vcc, .q=Q[0], .reset=gnd, :initv="0");
    inv INV_1 (.i=load, .o=N00194);
    inv INV_2 (.i=load, .o=N00213);
    inv INV_3 (.i=load, .o=N00257);
    inv INV_4 (.i=load, .o=N00274);
    inv INV_5 (.i=load, .o=N00300);
    inv INV_6 (.i=load, .o=N00317);
    inv INV_7 (.i=load, .o=N00334);
    inv INV_8 (.i=load, .o=N000610);
    or2 OR2_1 (.i0=N00248, .i1=N00198, .o=N000030);
    or2 OR2_2 (.i0=N00239, .i1=N00220, .o=N000050);
    or2 OR2_3 (.i0=N00261, .i1=N00265, .o=N000070);
    or2 OR2_4 (.i0=N00278, .i1=N00283, .o=N000090);
    or2 OR2_5 (.i0=N00304, .i1=N00308, .o=N000110);
    or2 OR2_6 (.i0=N00321, .i1=N00325, .o=N000130);
    or2 OR2_7 (.i0=N00338, .i1=N00342, .o=N000150);
    or2 OR2_8 (.i0=N00352, .i1=N000922, .o=N000170);
    or2 OR2_9 (.i0=N007281, .i1=loadcp, .o=N00745);
}