em78x447xx.h

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/**********************************************************
 *	Header file for the Elan 							  *	
 *	EM78P447SA chip										  *	
 *	EM78P447SB chip             						  *	
 *	Tilte:       EM78x447x include file					  *	
 *	Description: The Definition of EM78x447 Registers	  *  
 *	Company:     ELAN MICROELECTRONICS (SZ) LTD.		  *	         
 *	Author:      hongxi.tang                  			  * 
 *	Date:        20/05/2005                    			  *	
 *	Version:     v1.0                          			  *
 **********************************************************/
 
static unsigned int TCC     @0x01;
static unsigned int PC      @0x02;
static unsigned int STATUS  @0x03;
static unsigned int RSR     @0x04;
/*
RBS1     ==    0x07    ; R20~R3E ram bank select bit[1]
RBS0     ==    0x06    ; R20~R3E ram bank select bit[0]
                       ;
                       ; |------|------|-----------------------|
                       ; | RBS1 | RBS0 | Register Bank (20~3E) |
                       ; |------|------|-----------------------|
                       ; |  0   |  0   |        Bank 0         |
                       ; |  0   |  1   |        Bank 1         |
                       ; |  1   |  0   |        Bank 2         |
                       ; |  1   |  1   |        Bank 3         |
                       ; |------|------|-----------------------|
*/
static unsigned int PORT5   @0x05;
static unsigned int PORT6   @0x06;
static unsigned int PORT7   @0x07;
/*
;
; R3F/ISR: Interrupt Status Register
;
 R3F    ==    0x3F
 ISR    ==    0x3F
;
     ;{
                                ; Bits 7~4,2,1 not used
         EXIF     ==    0x03    ; External interrupt flag
         TCIF     ==    0x00    ; TCC overflow interrupt flag
                                ;
         mEXIF    ==    0x08    ; External interrupt flag
         mTCIF    ==    0x01    ; TCC overflow interupt flag
     ;}
;
;======================================================;
; Special Purpose Registers Define                     ;
;======================================================;
;
; A: Accumulator
; It can't be addressed.
;
; CONT: Control Register
;
     ;{
         mPHENB    ==    0x80    ; Control bit used to enable the pull-high of P60-P67,P74 and P75 pins
                                 ; "0" : Enable internal pull-high
                                 ; "1" : Disable internal pull-high
         mINTB     ==    0x40    ; Interrupt enable flag
                                 ; "0" : Masked by DISI or hardware interrupt
                                 ; "1" : Enabled by ENI/RETI instructions
         mTS       ==    0x20    ; TCC signal source
                                 ; "0" : Internal instruction cycle clock
                                 ; "1" : Transition on TCC pin
         mTE       ==    0x10    ; TCC signal edge
                                 ; "0" : Increment if the transition from low to high takes place on TCC pin
                                 ; "1" : Increment if the transition from high to low takes place on TCC pin
         mPAB      ==    0x08    ; Prescaler assignment bit
                                 ; "0" : Prescaler assign to TCC
                                 ; "1" : Prescaler assign to WDT
         mPSR2     ==    0x04    ; TCC/WDT prescaler Select bit[2]
         mPSR1     ==    0x02    ; TCC/WDT prescaler Select bit[1]
         mPSR0     ==    0x01    ; TCC/WDT prescaler Select bit[0]
                                 ; |------|------|------|----------|----------|
                                 ; | PSR2 | PSR1 | PSR0 | TCC Rate | WDT Rate |
                                 ; |------|------|------|----------|----------|
                                 ; |  0   |  0   |  0   |   1:2    |   1:1    |
                                 ; |  0   |  0   |  1   |   1:4    |   1:2    |
                                 ; |  0   |  1   |  0   |   1:8    |   1:4    |
                                 ; |  0   |  1   |  1   |   1:16   |   1:8    |
                                 ; |  1   |  0   |  0   |   1:32   |   1:16   |
                                 ; |  1   |  0   |  1   |   1:64   |   1:32   |
                                 ; |  1   |  1   |  0   |   1:128  |   1:64   |
                                 ; |  1   |  1   |  1   |   1:256  |   1:128  |
                                 ; |------|------|------|---------------------|
     ;}
;
*/

static io unsigned int P5CR		@0x05:iopage 0;
static io unsigned int P6CR		@0x06:iopage 0;
static io unsigned int P7CR		@0x07:iopage 0;
static io unsigned int WUCR		@0x0B:iopage 0;//Wake-up Control Register for port6 
static io unsigned int WDTCR	@0x0E:iopage 0;//WDT Control Register
static io unsigned int IMR		@0x0F:iopage 0;//Interrupt Mask Register
 
/*	STATUS bits	*/
static bit PS1 @0x03@6:rpage 0;
static bit PS0 @0x03@5:rpage 0;
/*
PS1     ==    0x06    ;
PS0     ==    0x05    ; (PS0~PS1): Page Select Bits
                      ; |-----|-----|-------------------------------|
                      ; | PS1 | PS0 | Program memory page [Address] |
                      ; |-----|-----|-------------------------------|
                      ; |  0  |  0  |       Page 0 [000 - 3FF]      |
                      ; |  0  |  1  |       Page 1 [400 - 7FF]      |
                      ; |  1  |  0  |       Page 2 [800 - BFF]      |
                      ; |  1  |  1  |       Page 3 [C00 - FFF]      |
                      ; |-----|-----|------------------------------ |
*/
static bit T   @0x03@4:rpage 0;
static bit P   @0x03@3:rpage 0;
static bit Z   @0x03@2:rpage 0;
static bit DC  @0x03@1:rpage 0;
static bit C   @0x03@0:rpage 0;
 
/*	PORT5 bits	*/
static bit R57	@0x05@7:rpage 0;
static bit R56	@0x05@6:rpage 0;
static bit R55	@0x05@5:rpage 0;
static bit R54 	@0x05@4:rpage 0;
static bit R53 	@0x05@3:rpage 0;
static bit R52 	@0x05@2:rpage 0;
static bit R51 	@0x05@1:rpage 0;
static bit R50 	@0x05@0:rpage 0;
 
/*	PORT6 bits	*/
static bit R67	@0x06@7:rpage 0;
static bit R66 	@0x06@6:rpage 0;
static bit R65 	@0x06@5:rpage 0;
static bit R64 	@0x06@4:rpage 0;
static bit R63 	@0x06@3:rpage 0;
static bit R62 	@0x06@2:rpage 0;
static bit R61 	@0x06@1:rpage 0;
static bit R60 	@0x06@0:rpage 0;
 
/*	PORT7 bits	*/
static bit R77 	@0x07@7:rpage 0;
static bit R76 	@0x07@6:rpage 0;
static bit R75 	@0x07@5:rpage 0;
static bit R74 	@0x07@4:rpage 0;
static bit R73 	@0x07@3:rpage 0;
static bit R72 	@0x07@2:rpage 0;
static bit R71 	@0x07@1:rpage 0;
static bit R70 	@0x07@0:rpage 0;