wbs_ram.v

这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序

//  successfully read and write!

module wbs_ram(

	// Clock and reset
	wb_clk_i, wb_rst_i,

	// WISHBONE Slave I/F
	wbs_cyc_i, wbs_stb_i, wbs_sel_i, wbs_we_i,
	wbs_adr_i, wbs_dat_i, wbs_cti_i,wbs_bte_i,
	wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o

);

// Clock and reset
//
input			wb_clk_i;	// Wishbone Clock
input			wb_rst_i;	// Reset

//
// WISHBONE Slave I/F
//
input			wbs_cyc_i;
input			wbs_stb_i;
input	[3:0]	wbs_sel_i;
input			wbs_we_i;
input	[31:0]	wbs_adr_i;
input	[31:0]	wbs_dat_i;
input			wbs_cti_i,wbs_bte_i;
output	[31:0]	wbs_dat_o;
output			wbs_ack_o;
output			wbs_err_o;
output			wbs_rty_o;


  reg			wbs_ack_o;	// WISHBONE ack
  reg			wbs_err_o;	// WISHBONE err

  wire          en1,en2,en10,en11,en12,en13;
  wire          wea;		  //write
  wire          web;		  //read
 
  wire   [31:0] dataout;
  wire   [6:0]	 addr;		 //128DWord
 
 

//  assign  wbs_dat_o = 32'h12345678;

//assign  wbs_dat_o = (!wbs_we_i) ? 32'h12345678 : 32'bz;

  assign  wbs_dat_o = (!wbs_we_i) ? dataout : 32'bz;	 //target read!

  assign  en1=wbs_cyc_i & wbs_stb_i;
  assign  en10=en1&(wbs_sel_i[0]);
  assign  en11=en1&(wbs_sel_i[1]);
  assign  en12=en1&(wbs_sel_i[2]);
  assign  en13=en1&(wbs_sel_i[3]);
  assign  wea=en1&wbs_we_i;


  assign  en2=1'b1;
  assign  web=1'b0;		    
  assign  addr=wbs_adr_i[8:2];
  
   
  assign wbs_rty_o = 1'b0;


  // assign   wbs_ack_o = 1'b1;
  // assign   wbs_err_o = 1'b0;


  //
// Generate delayed WISHBONE ack/err
//


always @(posedge wb_clk_i or posedge wb_rst_i)
	if (wb_rst_i) begin
		wbs_ack_o <=  1'b0;
		wbs_err_o <=  1'b0;
	end

	else if (wbs_cyc_i & wbs_stb_i) begin
		wbs_ack_o <=  1'b1;
		wbs_err_o <=  1'b0;
	end
	else begin
		wbs_ack_o <=  1'b0;
		wbs_err_o <=  1'b0;
	end



dpramb dpramb0(
	.addra(addr),
	.addrb(addr),
	.clka(wb_clk_i),
	.clkb(wb_clk_i),
	.dina(wbs_dat_i[7:0]),
//	.dinb(),
//	.douta(),
	.doutb(dataout[7:0]),
	.ena(en10),
	.enb(en2),
	.wea(wea),
	.web(web)
	);


dpramb dpramb1(
	.addra(addr),
	.addrb(addr),
	.clka(wb_clk_i),
	.clkb(wb_clk_i),
	.dina(wbs_dat_i[15:8]),
//	.dinb(),
//	.douta(),
	.doutb(dataout[15:8]),
	.ena(en11),
	.enb(en2),
	.wea(wea),
	.web(web)
	);


dpramb dpramb2(
	.addra(addr),
	.addrb(addr),
	.clka(wb_clk_i),
	.clkb(wb_clk_i),
	.dina(wbs_dat_i[23:16]),
//	.dinb(),
//	.douta(),
	.doutb(dataout[23:16]),
	.ena(en12),
	.enb(en2),
	.wea(wea),
	.web(web)
	);


dpramb dpramb3(
	.addra(addr),
	.addrb(addr),
	.clka(wb_clk_i),
	.clkb(wb_clk_i),
	.dina(wbs_dat_i[31:24]),
//	.dinb(),
//	.douta(),
	.doutb(dataout[31:24]),
	.ena(en13),
	.enb(en2),
	.wea(wea),
	.web(web)
	);
  


endmodule