wbs_uart.fse

来自「这是用pci-wishbone核和16450串口核在xilinx的fpga上实现」· FSE 代码 · 共 53 行

fsm_encoding {119501951} sequential

fsm_state_encoding {119501951} 00 {00}

fsm_state_encoding {119501951} 01 {01}

fsm_state_encoding {119501951} 10 {10}

fsm_registers {119501951} {wbstate[1]}  {wbstate[0]} 

fsm_encoding {621302132} onehot

fsm_state_encoding {621302132} s_idle {000001}

fsm_state_encoding {621302132} s_send_start {000010}

fsm_state_encoding {621302132} s_send_byte {000100}

fsm_state_encoding {621302132} s_send_parity {001000}

fsm_state_encoding {621302132} s_send_stop {010000}

fsm_state_encoding {621302132} s_pop_byte {100000}

fsm_registers {621302132} {tstate_1[5]}  {tstate_1[4]}  {tstate_1[3]}  {tstate_1[2]}  {tstate_1[1]}  {tstate_1[0]} 

fsm_encoding {1027502753} onehot

fsm_state_encoding {1027502753} sr_idle {00000000001}

fsm_state_encoding {1027502753} sr_rec_start {00000000010}

fsm_state_encoding {1027502753} sr_rec_bit {00000000100}

fsm_state_encoding {1027502753} sr_rec_parity {00000001000}

fsm_state_encoding {1027502753} sr_rec_stop {00000010000}

fsm_state_encoding {1027502753} sr_check_parity {00000100000}

fsm_state_encoding {1027502753} sr_rec_prepare {00001000000}

fsm_state_encoding {1027502753} sr_end_bit {00010000000}

fsm_state_encoding {1027502753} sr_ca_lc_parity {00100000000}

fsm_state_encoding {1027502753} sr_wait1 {01000000000}

fsm_state_encoding {1027502753} sr_push {10000000000}

fsm_registers {1027502753} {rstate_1[10]}  {rstate_1[9]}  {rstate_1[8]}  {rstate_1[7]}  {rstate_1[6]}  {rstate_1[5]}  {rstate_1[4]}  {rstate_1[3]}  {rstate_1[2]}  {rstate_1[1]}  {rstate_1[0]}