pci_bridge32.vif

这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序

#
# Synplicity Verification Interface File
# Generated using Synplify-pro
#
# Copyright (c) 1996-2004 Synplicity, Inc.
# All rights reserved
#

# Set logfile options
vif_set_result_file  pci_bridge32.vlf

# RTL and technology files
vif_add_library -original $XILINX/verilog/verification/unisims
vif_add_library -original $XILINX/verilog/verification/simprims
vif_add_file -original  -verilog D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v
vif_add_file -original  -verilog ./pci_out_reg.v
vif_add_file -original  -verilog ./pci_constants.v
vif_add_file -original  -verilog ./pci_user_constants.v
vif_add_file -original  -verilog ./pci_rst_int.v
vif_add_file -original  -verilog ./pci_async_reset_flop.v
vif_add_file -original  -verilog ./pci_wb_slave.v
vif_add_file -original  -verilog ./bus_commands.v
vif_add_file -original  -verilog ./pci_wb_tpram.v
vif_add_file -original  -verilog ./pci_synchronizer_flop.v
vif_add_file -original  -verilog ./pci_wbw_fifo_control.v
vif_add_file -original  -verilog ./pci_wbr_fifo_control.v
vif_add_file -original  -verilog ./pci_wbw_wbr_fifos.v
vif_add_file -original  -verilog ./pci_wb_decoder.v
vif_add_file -original  -verilog ./pci_wb_addr_mux.v
vif_add_file -original  -verilog ./pci_delayed_sync.v
vif_add_file -original  -verilog ./pci_delayed_write_reg.v
vif_add_file -original  -verilog ./pci_master32_sm_if.v
vif_add_file -original  -verilog ./pci_frame_crit.v
vif_add_file -original  -verilog ./pci_frame_load_crit.v
vif_add_file -original  -verilog ./pci_irdy_out_crit.v
vif_add_file -original  -verilog ./pci_mas_ad_load_crit.v
vif_add_file -original  -verilog ./pci_mas_ch_state_crit.v
vif_add_file -original  -verilog ./pci_mas_ad_en_crit.v
vif_add_file -original  -verilog ./pci_cbe_en_crit.v
vif_add_file -original  -verilog ./pci_frame_en_crit.v
vif_add_file -original  -verilog ./pci_master32_sm.v
vif_add_file -original  -verilog ./pci_wb_slave_unit.v
vif_add_file -original  -verilog ./pci_wb_master.v
vif_add_file -original  -verilog ./pci_pci_tpram.v
vif_add_file -original  -verilog ./pci_pciw_fifo_control.v
vif_add_file -original  -verilog ./pci_pcir_fifo_control.v
vif_add_file -original  -verilog ./pci_pciw_pcir_fifos.v
vif_add_file -original  -verilog ./pci_pci_decoder.v
vif_add_file -original  -verilog ./pci_target32_interface.v
vif_add_file -original  -verilog ./pci_target32_clk_en.v
vif_add_file -original  -verilog ./pci_target32_trdy_crit.v
vif_add_file -original  -verilog ./pci_target32_stop_crit.v
vif_add_file -original  -verilog ./pci_target32_devs_crit.v
vif_add_file -original  -verilog ./pci_target32_sm.v
vif_add_file -original  -verilog ./pci_target_unit.v
vif_add_file -original  -verilog ./pci_sync_module.v
vif_add_file -original  -verilog ./pci_conf_space.v
vif_add_file -original  -verilog ./pci_io_mux_ad_en_crit.v
vif_add_file -original  -verilog ./pci_io_mux_ad_load_crit.v
vif_add_file -original  -verilog ./pci_io_mux.v
vif_add_file -original  -verilog ./pci_cur_out_reg.v
vif_add_file -original  -verilog ./pci_par_crit.v
vif_add_file -original  -verilog ./pci_perr_crit.v
vif_add_file -original  -verilog ./pci_perr_en_crit.v
vif_add_file -original  -verilog ./pci_serr_en_crit.v
vif_add_file -original  -verilog ./pci_serr_crit.v
vif_add_file -original  -verilog ./pci_parity_check.v
vif_add_file -original  -verilog ./pci_in_reg.v
vif_add_file -original  -verilog ./pci_bridge32.v
vif_set_top_module -original -top pci_bridge32
 
vif_add_library -translated $XILINX/verilog/verification/unisims
vif_add_library -translated $XILINX/verilog/verification/simprims
vif_add_file -translated -verilog pci_bridge32.vm
vif_set_top_module -translated -top pci_bridge32 


# Read FSM encoding
vif_set_fsm -fsm fsm_0
vif_set_fsmreg -original -fsm fsm_0 wishbone_slave_unit/wishbone_slave/c_state_Z[2:0]
vif_set_fsmreg -translated -fsm  fsm_0 wishbone_slave_unit/wishbone_slave/c_state_Z[5:0]
vif_set_state_map -fsm fsm_0 -original "000" -translated "000001"
vif_set_state_map -fsm fsm_0 -original "011" -translated "000010"
vif_set_state_map -fsm fsm_0 -original "100" -translated "000100"
vif_set_state_map -fsm fsm_0 -original "101" -translated "001000"
vif_set_state_map -fsm fsm_0 -original "110" -translated "010000"
vif_set_state_map -fsm fsm_0 -original "111" -translated "100000"
vif_set_fsm -fsm fsm_1
vif_set_fsmreg -original -fsm fsm_1 wishbone_slave_unit/wishbone_slave/c_state_Z[2:0]
vif_set_fsmreg -translated -fsm  fsm_1 wishbone_slave_unit/wishbone_slave/c_state_Z[5:0]
vif_set_state_map -fsm fsm_1 -original "000" -translated "000001"
vif_set_state_map -fsm fsm_1 -original "011" -translated "000010"
vif_set_state_map -fsm fsm_1 -original "100" -translated "000100"
vif_set_state_map -fsm fsm_1 -original "101" -translated "001000"
vif_set_state_map -fsm fsm_1 -original "110" -translated "010000"
vif_set_state_map -fsm fsm_1 -original "111" -translated "100000"
vif_set_fsm -fsm fsm_6
vif_set_fsmreg -original -fsm fsm_6 wishbone_slave_unit/pci_initiator_sm/cur_state_Z[3:0]
vif_set_fsmreg -translated -fsm  fsm_6 wishbone_slave_unit/pci_initiator_sm/cur_state_Z[1:0]
vif_set_state_map -fsm fsm_6 -original "0001" -translated "00"
vif_set_state_map -fsm fsm_6 -original "0010" -translated "01"
vif_set_state_map -fsm fsm_6 -original "0100" -translated "10"
vif_set_state_map -fsm fsm_6 -original "1000" -translated "11"
vif_set_fsm -fsm fsm_9
vif_set_fsmreg -original -fsm fsm_9 pci_target_unit/wishbone_master/c_state_Z[2:0]
vif_set_fsmreg -translated -fsm  fsm_9 pci_target_unit/wishbone_master/c_state_Z[5:0]
vif_set_state_map -fsm fsm_9 -original "000" -translated "000001"
vif_set_state_map -fsm fsm_9 -original "001" -translated "000010"
vif_set_state_map -fsm fsm_9 -original "010" -translated "000100"
vif_set_state_map -fsm fsm_9 -original "011" -translated "001000"
vif_set_state_map -fsm fsm_9 -original "100" -translated "010000"
vif_set_state_map -fsm fsm_9 -original "101" -translated "100000"
vif_set_fsm -fsm fsm_16
vif_set_fsmreg -original -fsm fsm_16 pci_target_unit/pci_target_sm/c_state_Z[2:0]
vif_set_fsmreg -translated -fsm  fsm_16 pci_target_unit/pci_target_sm/c_state_Z[1:0]
vif_set_state_map -fsm fsm_16 -original "001" -translated "00"
vif_set_state_map -fsm fsm_16 -original "010" -translated "01"
vif_set_state_map -fsm fsm_16 -original "100" -translated "10"


# Memory map points
# Memory redundancies