top.vif

这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序

#
# Synplicity Verification Interface File
# Generated using Synplify-pro
#
# Copyright (c) 1996-2004 Synplicity, Inc.
# All rights reserved
#

# Set logfile options
vif_set_result_file  TOP.vlf

# RTL and technology files
vif_add_library -original $XILINX/verilog/verification/unisims
vif_add_library -original $XILINX/verilog/verification/simprims
vif_add_file -original  -verilog C:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v
vif_add_file -original  -verilog ./pci_out_reg.v
vif_add_file -original  -verilog ./pci_constants.v
vif_add_file -original  -verilog ./pci_user_constants.v
vif_add_file -original  -verilog ./pci_rst_int.v
vif_add_file -original  -verilog ./pci_async_reset_flop.v
vif_add_file -original  -verilog ./pci_wb_slave.v
vif_add_file -original  -verilog ./bus_commands.v
vif_add_file -original  -verilog ./pci_wb_tpram.v
vif_add_file -original  -verilog ./pci_synchronizer_flop.v
vif_add_file -original  -verilog ./pci_wbw_fifo_control.v
vif_add_file -original  -verilog ./pci_wbr_fifo_control.v
vif_add_file -original  -verilog ./pci_wbw_wbr_fifos.v
vif_add_file -original  -verilog ./pci_wb_decoder.v
vif_add_file -original  -verilog ./pci_wb_addr_mux.v
vif_add_file -original  -verilog ./pci_delayed_sync.v
vif_add_file -original  -verilog ./pci_delayed_write_reg.v
vif_add_file -original  -verilog ./pci_master32_sm_if.v
vif_add_file -original  -verilog ./pci_frame_crit.v
vif_add_file -original  -verilog ./pci_frame_load_crit.v
vif_add_file -original  -verilog ./pci_irdy_out_crit.v
vif_add_file -original  -verilog ./pci_mas_ad_load_crit.v
vif_add_file -original  -verilog ./pci_mas_ch_state_crit.v
vif_add_file -original  -verilog ./pci_mas_ad_en_crit.v
vif_add_file -original  -verilog ./pci_cbe_en_crit.v
vif_add_file -original  -verilog ./pci_frame_en_crit.v
vif_add_file -original  -verilog ./pci_master32_sm.v
vif_add_file -original  -verilog ./pci_wb_slave_unit.v
vif_add_file -original  -verilog ./pci_wb_master.v
vif_add_file -original  -verilog ./pci_pci_tpram.v
vif_add_file -original  -verilog ./pci_pciw_fifo_control.v
vif_add_file -original  -verilog ./pci_pcir_fifo_control.v
vif_add_file -original  -verilog ./pci_pciw_pcir_fifos.v
vif_add_file -original  -verilog ./pci_pci_decoder.v
vif_add_file -original  -verilog ./pci_target32_interface.v
vif_add_file -original  -verilog ./pci_target32_clk_en.v
vif_add_file -original  -verilog ./pci_target32_trdy_crit.v
vif_add_file -original  -verilog ./pci_target32_stop_crit.v
vif_add_file -original  -verilog ./pci_target32_devs_crit.v
vif_add_file -original  -verilog ./pci_target32_sm.v
vif_add_file -original  -verilog ./pci_target_unit.v
vif_add_file -original  -verilog ./pci_sync_module.v
vif_add_file -original  -verilog ./pci_conf_space.v
vif_add_file -original  -verilog ./pci_io_mux_ad_en_crit.v
vif_add_file -original  -verilog ./pci_io_mux_ad_load_crit.v
vif_add_file -original  -verilog ./pci_io_mux.v
vif_add_file -original  -verilog ./pci_cur_out_reg.v
vif_add_file -original  -verilog ./pci_par_crit.v
vif_add_file -original  -verilog ./pci_perr_crit.v
vif_add_file -original  -verilog ./pci_perr_en_crit.v
vif_add_file -original  -verilog ./pci_serr_en_crit.v
vif_add_file -original  -verilog ./pci_serr_crit.v
vif_add_file -original  -verilog ./pci_parity_check.v
vif_add_file -original  -verilog ./pci_in_reg.v
vif_add_file -original  -verilog ./pci_bridge32.v
vif_add_file -original  -verilog ./WB_Slave.v
vif_add_file -original  -verilog ./WB_Master.v
vif_add_file -original  -verilog ./top.v
vif_set_top_module -original -top TOP
 
vif_add_library -translated $XILINX/verilog/verification/unisims
vif_add_library -translated $XILINX/verilog/verification/simprims
vif_add_file -translated -verilog TOP.vm
vif_set_top_module -translated -top TOP 


# Read FSM encoding
vif_set_fsm -fsm fsm_0
vif_set_fsmreg -original -fsm fsm_0 bridge/wishbone_slave_unit/wishbone_slave/c_state_Z[2:0]
vif_set_fsmreg -translated -fsm  fsm_0 bridge/wishbone_slave_unit/wishbone_slave/c_state_Z[5:0]
vif_set_state_map -fsm fsm_0 -original "000" -translated "000001"
vif_set_state_map -fsm fsm_0 -original "011" -translated "000010"
vif_set_state_map -fsm fsm_0 -original "100" -translated "000100"
vif_set_state_map -fsm fsm_0 -original "101" -translated "001000"
vif_set_state_map -fsm fsm_0 -original "110" -translated "010000"
vif_set_state_map -fsm fsm_0 -original "111" -translated "100000"
vif_set_fsm -fsm fsm_1
vif_set_fsmreg -original -fsm fsm_1 bridge/wishbone_slave_unit/wishbone_slave/c_state_Z[2:0]
vif_set_fsmreg -translated -fsm  fsm_1 bridge/wishbone_slave_unit/wishbone_slave/c_state_Z[5:0]
vif_set_state_map -fsm fsm_1 -original "000" -translated "000001"
vif_set_state_map -fsm fsm_1 -original "011" -translated "000010"
vif_set_state_map -fsm fsm_1 -original "100" -translated "000100"
vif_set_state_map -fsm fsm_1 -original "101" -translated "001000"
vif_set_state_map -fsm fsm_1 -original "110" -translated "010000"
vif_set_state_map -fsm fsm_1 -original "111" -translated "100000"
vif_set_fsm -fsm fsm_6
vif_set_fsmreg -original -fsm fsm_6 bridge/wishbone_slave_unit/pci_initiator_sm/cur_state_Z[3:0]
vif_set_fsmreg -translated -fsm  fsm_6 bridge/wishbone_slave_unit/pci_initiator_sm/cur_state_Z[1:0]
vif_set_state_map -fsm fsm_6 -original "0001" -translated "00"
vif_set_state_map -fsm fsm_6 -original "0010" -translated "01"
vif_set_state_map -fsm fsm_6 -original "0100" -translated "10"
vif_set_state_map -fsm fsm_6 -original "1000" -translated "11"
vif_set_fsm -fsm fsm_9
vif_set_fsmreg -original -fsm fsm_9 bridge/pci_target_unit/wishbone_master/c_state_Z[2:0]
vif_set_fsmreg -translated -fsm  fsm_9 bridge/pci_target_unit/wishbone_master/c_state_Z[5:0]
vif_set_state_map -fsm fsm_9 -original "000" -translated "000001"
vif_set_state_map -fsm fsm_9 -original "001" -translated "000010"
vif_set_state_map -fsm fsm_9 -original "010" -translated "000100"
vif_set_state_map -fsm fsm_9 -original "011" -translated "001000"
vif_set_state_map -fsm fsm_9 -original "100" -translated "010000"
vif_set_state_map -fsm fsm_9 -original "101" -translated "100000"
vif_set_fsm -fsm fsm_10
vif_set_fsmreg -original -fsm fsm_10 bridge/pci_target_unit/wishbone_master/c_state_Z[2:0]
vif_set_fsmreg -translated -fsm  fsm_10 bridge/pci_target_unit/wishbone_master/c_state_Z[5:0]
vif_set_state_map -fsm fsm_10 -original "000" -translated "000001"
vif_set_state_map -fsm fsm_10 -original "001" -translated "000010"
vif_set_state_map -fsm fsm_10 -original "010" -translated "000100"
vif_set_state_map -fsm fsm_10 -original "011" -translated "001000"
vif_set_state_map -fsm fsm_10 -original "100" -translated "010000"
vif_set_state_map -fsm fsm_10 -original "101" -translated "100000"
vif_set_fsm -fsm fsm_16
vif_set_fsmreg -original -fsm fsm_16 bridge/pci_target_unit/pci_target_sm/c_state_Z[2:0]
vif_set_fsmreg -translated -fsm  fsm_16 bridge/pci_target_unit/pci_target_sm/c_state_Z[1:0]
vif_set_state_map -fsm fsm_16 -original "001" -translated "00"
vif_set_state_map -fsm fsm_16 -original "010" -translated "01"
vif_set_state_map -fsm fsm_16 -original "100" -translated "10"
vif_set_fsm -fsm fsm_19
vif_set_fsmreg -original -fsm fsm_19 wb_master_inst/state_Z[1:0]
vif_set_fsmreg -translated -fsm  fsm_19 wb_master_inst/state_Z[1:0]
vif_set_state_map -fsm fsm_19 -original "00" -translated "00"
vif_set_state_map -fsm fsm_19 -original "01" -translated "01"
vif_set_state_map -fsm fsm_19 -original "10" -translated "10"
vif_set_state_map -fsm fsm_19 -original "11" -translated "11"


# Memory map points
# Memory redundancies


# SRL redundancies
# SRL map points


# RTL sequential redundancies
vif_set_merge -original bridge/wishbone_slave_unit/wishbone_slave/d_incoming_Z[35] bridge/wishbone_slave_unit/wishbone_slave/d_incoming_Z[32]
vif_set_merge -original bridge/wishbone_slave_unit/wishbone_slave/d_incoming_Z[35] bridge/wishbone_slave_unit/wishbone_slave/d_incoming_Z[33]
vif_set_merge -original bridge/wishbone_slave_unit/wishbone_slave/d_incoming_Z[35] bridge/wishbone_slave_unit/wishbone_slave/d_incoming_Z[34]
vif_set_merge -original bridge/wishbone_slave_unit/del_sync/be_out_Z[3] bridge/wishbone_slave_unit/del_sync/be_out_Z[0]
vif_set_merge -original bridge/wishbone_slave_unit/del_sync/be_out_Z[3] bridge/wishbone_slave_unit/del_sync/be_out_Z[1]
vif_set_merge -original bridge/wishbone_slave_unit/del_sync/be_out_Z[3] bridge/wishbone_slave_unit/del_sync/be_out_Z[2]
vif_set_merge -original -fsmopt bridge/wishbone_slave_unit/pci_initiator_sm/cur_state_Z[1] bridge/wishbone_slave_unit/pci_initiator_sm/rdata_selector_Z[1]
vif_set_merge -original bridge/pci_target_unit/pci_target_if/norm_bc_Z[0] bridge/pci_target_unit/pci_target_sm/bc0_out_Z
vif_set_merge -original bridge/pci_target_unit/pci_target_if/strd_address_Z[11] bridge/pci_target_unit/pci_target_if/addr_out_Z[11]
vif_set_merge -original bridge/pci_target_unit/pci_target_if/strd_address_Z[10] bridge/pci_target_unit/pci_target_if/addr_out_Z[10]
vif_set_merge -original bridge/pci_target_unit/pci_target_if/strd_address_Z[9] bridge/pci_target_unit/pci_target_if/addr_out_Z[9]
vif_set_merge -original bridge/pci_target_unit/pci_target_if/strd_address_Z[8] bridge/pci_target_unit/pci_target_if/addr_out_Z[8]
vif_set_merge -original bridge/pci_target_unit/pci_target_if/strd_address_Z[7] bridge/pci_target_unit/pci_target_if/addr_out_Z[7]
vif_set_merge -original bridge/pci_target_unit/pci_target_if/strd_address_Z[6] bridge/pci_target_unit/pci_target_if/addr_out_Z[6]
vif_set_merge -original bridge/pci_target_unit/pci_target_if/strd_address_Z[5] bridge/pci_target_unit/pci_target_if/addr_out_Z[5]
vif_set_merge -original bridge/pci_target_unit/pci_target_if/strd_address_Z[4] bridge/pci_target_unit/pci_target_if/addr_out_Z[4]
vif_set_merge -original bridge/pci_target_unit/pci_target_if/strd_address_Z[3] bridge/pci_target_unit/pci_target_if/addr_out_Z[3]
vif_set_merge -original bridge/pci_target_unit/pci_target_if/strd_address_Z[2] bridge/pci_target_unit/pci_target_if/addr_out_Z[2]
vif_set_merge -original bridge/pci_target_unit/pci_target_if/strd_address_Z[1] bridge/pci_target_unit/pci_target_if/addr_out_Z[1]
vif_set_merge -original bridge/pci_target_unit/pci_target_if/strd_address_Z[0] bridge/pci_target_unit/pci_target_if/addr_out_Z[0]
vif_set_merge -original bridge/pci_target_unit/pci_target_if/same_read_reg_Z bridge/pci_target_unit/pci_target_sm/same_read_reg_Z
vif_set_merge -original bridge/configuration/sync_pci_err_cs_8/delayed_del_bit_Z bridge/configuration/sync_pci_err_cs_8/clear_delete_sync/sync_data_out_Z[0]
vif_set_merge -original bridge/configuration/sync_isr_2/delayed_del_bit_Z bridge/configuration/sync_isr_2/clear_delete_sync/sync_data_out_Z[0]
vif_set_merge -original bridge/pci_io_mux/ad_iob0/dat_out_Z bridge/output_backup/ad_out_Z[0]
vif_set_merge -original bridge/pci_io_mux/ad_iob1/dat_out_Z bridge/output_backup/ad_out_Z[1]
vif_set_merge -original bridge/pci_io_mux/ad_iob2/dat_out_Z bridge/output_backup/ad_out_Z[2]
vif_set_merge -original bridge/pci_io_mux/ad_iob3/dat_out_Z bridge/output_backup/ad_out_Z[3]
vif_set_merge -original bridge/pci_io_mux/ad_iob4/dat_out_Z bridge/output_backup/ad_out_Z[4]
vif_set_merge -original bridge/pci_io_mux/ad_iob5/dat_out_Z bridge/output_backup/ad_out_Z[5]
vif_set_merge -original bridge/pci_io_mux/ad_iob6/dat_out_Z bridge/output_backup/ad_out_Z[6]
vif_set_merge -original bridge/pci_io_mux/ad_iob7/dat_out_Z bridge/output_backup/ad_out_Z[7]
vif_set_merge -original bridge/pci_io_mux/ad_iob8/dat_out_Z bridge/output_backup/ad_out_Z[8]
vif_set_merge -original bridge/pci_io_mux/ad_iob9/dat_out_Z bridge/output_backup/ad_out_Z[9]
vif_set_merge -original bridge/pci_io_mux/ad_iob10/dat_out_Z bridge/output_backup/ad_out_Z[10]
vif_set_merge -original bridge/pci_io_mux/ad_iob11/dat_out_Z bridge/output_backup/ad_out_Z[11]
vif_set_merge -original bridge/pci_io_mux/ad_iob12/dat_out_Z bridge/output_backup/ad_out_Z[12]