pci_pciw_pcir_fifos.v

这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序

/*-----------------------------------------------------------------------------------------------------------
wires monitoring control bus. When control bus on a write transaction has a value of `LAST, it means that
complete transaction is in the FIFO. When control bus on a read transaction has a value of `LAST,
it means that there was one complete transaction taken out of FIFO.
-----------------------------------------------------------------------------------------------------------*/
wire pciw_last_in  = pciw_control_in[`LAST_CTRL_BIT] ;
wire pciw_last_out = pciw_control_out[`LAST_CTRL_BIT] ;

/*wire pcir_last_in  = pcir_wallow && (pcir_control_in == `LAST) ;
wire pcir_last_out = pcir_rallow && (pcir_control_out == `LAST) ;*/

wire pciw_empty ;
wire pcir_empty ;

assign pciw_empty_out = pciw_empty ;
assign pcir_empty_out = pcir_empty ;

// clear wires for clearing FFs and registers
wire pciw_clear = reset_in /*|| pciw_flush_in*/ ; // PCIW_FIFO's clear signal - flush not used
wire pcir_clear = reset_in /*|| pcir_flush_in*/ ; // PCIR_FIFO's clear signal - flush changed to synchronous op.

/*-----------------------------------------------------------------------------------------------------------
Definitions of wires for connecting RAM instances
-----------------------------------------------------------------------------------------------------------*/
wire [39:0] dpram_portA_output ;
wire [39:0] dpram_portB_output ;

wire [39:0] dpram_portA_input = {pciw_control_in, pciw_cbe_in, pciw_addr_data_in} ;
wire [39:0] dpram_portB_input = {pcir_control_in, pcir_be_in, pcir_data_in} ;

/*-----------------------------------------------------------------------------------------------------------
Fifo output assignments - each ram port provides data for different fifo
-----------------------------------------------------------------------------------------------------------*/
assign pciw_control_out = dpram_portB_output[39:36] ;
assign pcir_control_out = dpram_portA_output[39:36] ;

assign pciw_cbe_out     = dpram_portB_output[35:32] ;
assign pcir_be_out      = dpram_portA_output[35:32] ;

assign pciw_addr_data_out = dpram_portB_output[31:0] ;
assign pcir_data_out      = dpram_portA_output[31:0] ;

`ifdef PCI_RAM_DONT_SHARE

    /*-----------------------------------------------------------------------------------------------------------
    Piece of code in this ifdef section is used in applications which can provide enough RAM instances to
    accomodate four fifos - each occupying its own instance of ram. Ports are connected in such a way,
    that instances of RAMs can be changed from two port to dual port ( async read/write port ). In that case,
    write port is always port a and read port is port b.
    -----------------------------------------------------------------------------------------------------------*/

    /*-----------------------------------------------------------------------------------------------------------
    Pad redundant address lines with zeros. This may seem stupid, but it comes in perfect for FPGA impl.
    -----------------------------------------------------------------------------------------------------------*/
    /*
    wire [(`PCIW_FIFO_RAM_ADDR_LENGTH - PCIW_ADDR_LENGTH - 1):0] pciw_addr_prefix = {( `PCIW_FIFO_RAM_ADDR_LENGTH - PCIW_ADDR_LENGTH){1'b0}} ;
    wire [(`PCIR_FIFO_RAM_ADDR_LENGTH - PCIR_ADDR_LENGTH - 1):0] pcir_addr_prefix = {( `PCIR_FIFO_RAM_ADDR_LENGTH - PCIR_ADDR_LENGTH){1'b0}} ;
    */

    // compose complete port addresses
    wire [(`PCI_FIFO_RAM_ADDR_LENGTH-1):0] pciw_whole_waddr = pciw_waddr ;
    wire [(`PCI_FIFO_RAM_ADDR_LENGTH-1):0] pciw_whole_raddr = pciw_raddr ;

    wire [(`PCI_FIFO_RAM_ADDR_LENGTH-1):0] pcir_whole_waddr = pcir_waddr ;
    wire [(`PCI_FIFO_RAM_ADDR_LENGTH-1):0] pcir_whole_raddr = pcir_raddr ;

    wire pciw_read_enable = 1'b1 ;
    wire pcir_read_enable = 1'b1 ;

    `ifdef PCI_BIST
    wire mbist_so_o_internal ; // wires for connection of debug ports on two rams
    wire mbist_si_i_internal = mbist_so_o_internal ;
    `endif

    // instantiate and connect two generic rams - one for pci write fifo and one for pci read fifo
    pci_pci_tpram #(`PCI_FIFO_RAM_ADDR_LENGTH, 40) pciw_fifo_storage
    (
        // Generic synchronous two-port RAM interface
        .clk_a(pci_clock_in),
        .rst_a(reset_in),
        .ce_a(1'b1),
        .we_a(pciw_wallow),
        .oe_a(1'b1),
        .addr_a(pciw_whole_waddr),
        .di_a(dpram_portA_input),
        .do_a(),

        .clk_b(wb_clock_in),
        .rst_b(reset_in),
        .ce_b(pciw_read_enable),
        .we_b(1'b0),
        .oe_b(1'b1),
        .addr_b(pciw_whole_raddr),
        .di_b(40'h00_0000_0000),
        .do_b(dpram_portB_output)

    `ifdef PCI_BIST
        ,
        .mbist_si_i       (mbist_si_i),
        .mbist_so_o       (mbist_so_o_internal),
        .mbist_ctrl_i       (mbist_ctrl_i)
    `endif
    );

    pci_pci_tpram #(`PCI_FIFO_RAM_ADDR_LENGTH, 40) pcir_fifo_storage
    (
        // Generic synchronous two-port RAM interface
        .clk_a(wb_clock_in),
        .rst_a(reset_in),
        .ce_a(1'b1),
        .we_a(pcir_wallow),
        .oe_a(1'b1),
        .addr_a(pcir_whole_waddr),
        .di_a(dpram_portB_input),
        .do_a(),

        .clk_b(pci_clock_in),
        .rst_b(reset_in),
        .ce_b(pcir_read_enable),
        .we_b(1'b0),
        .oe_b(1'b1),
        .addr_b(pcir_whole_raddr),
        .di_b(40'h00_0000_0000),
        .do_b(dpram_portA_output)

    `ifdef PCI_BIST
        ,
        .mbist_si_i       (mbist_si_i_internal),
        .mbist_so_o       (mbist_so_o),
        .mbist_ctrl_i       (mbist_ctrl_i)
    `endif
    );

`else // RAM blocks sharing between two fifos

    /*-----------------------------------------------------------------------------------------------------------
    Code section under this ifdef is used for implementation where RAM instances are too expensive. In this
    case one RAM instance is used for both - pci read and pci write fifo.
    -----------------------------------------------------------------------------------------------------------*/
    /*-----------------------------------------------------------------------------------------------------------
    Address prefix definition - since both FIFOs reside in same RAM instance, storage is separated by MSB
    addresses. pci write fifo addresses are padded with zeros on the MSB side ( at least one address line
    must be used for this ), pci read fifo addresses are padded with ones on the right ( at least one ).
    -----------------------------------------------------------------------------------------------------------*/
    wire [(`PCI_FIFO_RAM_ADDR_LENGTH - PCIW_ADDR_LENGTH - 1):0] pciw_addr_prefix = {( `PCI_FIFO_RAM_ADDR_LENGTH - PCIW_ADDR_LENGTH){1'b0}} ;
    wire [(`PCI_FIFO_RAM_ADDR_LENGTH - PCIR_ADDR_LENGTH - 1):0] pcir_addr_prefix = {( `PCI_FIFO_RAM_ADDR_LENGTH - PCIR_ADDR_LENGTH){1'b1}} ;

    /*-----------------------------------------------------------------------------------------------------------
    Port A address generation for RAM instance. RAM instance must be full two port RAM - read and write capability
    on both sides.
    Port A is clocked by PCI clock, DIA is input for pciw_fifo, DOA is output for pcir_fifo.
    Address is multiplexed so operation can be switched between fifos. Default is a read on port.
    -----------------------------------------------------------------------------------------------------------*/
    wire [(`PCI_FIFO_RAM_ADDR_LENGTH-1):0] portA_addr = pciw_wallow ? {pciw_addr_prefix, pciw_waddr} : {pcir_addr_prefix, pcir_raddr} ;

    /*-----------------------------------------------------------------------------------------------------------
    Port B is clocked by WISHBONE clock, DIB is input for pcir_fifo, DOB is output for pciw_fifo.
    Address is multiplexed so operation can be switched between fifos. Default is a read on port.
    -----------------------------------------------------------------------------------------------------------*/
    wire [(`PCI_FIFO_RAM_ADDR_LENGTH-1):0] portB_addr  = pcir_wallow ? {pcir_addr_prefix, pcir_waddr} : {pciw_addr_prefix, pciw_raddr} ;

    wire portA_enable      = 1'b1 ;

    wire portB_enable      = 1'b1 ;

    // instantiate RAM for these two fifos
    pci_pci_tpram #(`PCI_FIFO_RAM_ADDR_LENGTH, 40) pciu_fifo_storage
    (
        // Generic synchronous two-port RAM interface
        .clk_a(pci_clock_in),
        .rst_a(reset_in),
        .ce_a(portA_enable),
        .we_a(pciw_wallow),
        .oe_a(1'b1),
        .addr_a(portA_addr),
        .di_a(dpram_portA_input),
        .do_a(dpram_portA_output),
        .clk_b(wb_clock_in),
        .rst_b(reset_in),
        .ce_b(portB_enable),
        .we_b(pcir_wallow),
        .oe_b(1'b1),
        .addr_b(portB_addr),
        .di_b(dpram_portB_input),
        .do_b(dpram_portB_output)

    `ifdef PCI_BIST
        ,
        .mbist_si_i       (mbist_si_i),
        .mbist_so_o       (mbist_so_o),
        .mbist_ctrl_i       (mbist_ctrl_i)
    `endif
    );

`endif

/*-----------------------------------------------------------------------------------------------------------
Instantiation of two control logic modules - one for PCIW_FIFO and one for PCIR_FIFO
-----------------------------------------------------------------------------------------------------------*/
pci_pciw_fifo_control #(PCIW_ADDR_LENGTH) pciw_fifo_ctrl
(
    .rclock_in(wb_clock_in),
    .wclock_in(pci_clock_in),
    .renable_in(pciw_renable_in),
    .wenable_in(pciw_wenable_in),
    .reset_in(reset_in),
//    .flush_in(pciw_flush_in),                     // flush not used
    .three_left_out(pciw_three_left_out),
    .two_left_out(pciw_two_left_out),
    .almost_full_out(pciw_almost_full_out),
    .full_out(pciw_full_out),
    .almost_empty_out(pciw_almost_empty_out),
    .empty_out(pciw_empty),
    .waddr_out(pciw_waddr),
    .raddr_out(pciw_raddr),
    .rallow_out(pciw_rallow),
    .wallow_out(pciw_wallow)
);

pci_pcir_fifo_control #(PCIR_ADDR_LENGTH) pcir_fifo_ctrl
(
    .rclock_in(pci_clock_in),
    .wclock_in(wb_clock_in),
    .renable_in(pcir_renable_in),
    .wenable_in(pcir_wenable_in),
    .reset_in(reset_in),
    .flush_in(pcir_flush_in),
    .full_out(pcir_full_out),
    .almost_empty_out(pcir_almost_empty_out),
    .empty_out(pcir_empty),
    .waddr_out(pcir_waddr),
    .raddr_out(pcir_raddr),
    .rallow_out(pcir_rallow),
    .wallow_out(pcir_wallow)
);


// in and out transaction counters and grey codes
reg  [(PCIW_ADDR_LENGTH-2):0] inGreyCount ;
reg  [(PCIW_ADDR_LENGTH-2):0] outGreyCount ;
wire [(PCIW_ADDR_LENGTH-2):0] inNextGreyCount  = {pciw_inTransactionCount[(PCIW_ADDR_LENGTH-2)], pciw_inTransactionCount[(PCIW_ADDR_LENGTH-2):1] ^ pciw_inTransactionCount[(PCIW_ADDR_LENGTH-3):0]} ;
wire [(PCIW_ADDR_LENGTH-2):0] outNextGreyCount = {pciw_outTransactionCount[(PCIW_ADDR_LENGTH-2)], pciw_outTransactionCount[(PCIW_ADDR_LENGTH-2):1] ^ pciw_outTransactionCount[(PCIW_ADDR_LENGTH-3):0]} ;

// input transaction counter is incremented when whole transaction is written to fifo. This is indicated by last control bit written to last transaction location
wire in_count_en  = pciw_wallow && pciw_last_in ;

// output transaction counter is incremented when whole transaction is pulled out of fifo. This is indicated when location with last control bit set is read
wire out_count_en = pciw_rallow && pciw_last_out ;

always@(posedge pci_clock_in or posedge pciw_clear)
begin
    if (pciw_clear)
    begin
        inGreyCount <= 0 ;
    end
    else
    if (in_count_en)
        inGreyCount <= #`FF_DELAY inNextGreyCount ;
end

wire [(PCIW_ADDR_LENGTH-2):0] wb_clk_sync_inGreyCount ;
reg  [(PCIW_ADDR_LENGTH-2):0] wb_clk_inGreyCount ;
pci_synchronizer_flop #((PCIW_ADDR_LENGTH - 1), 0) i_synchronizer_reg_inGreyCount
(
    .data_in        (inGreyCount),
    .clk_out        (wb_clock_in),
    .sync_data_out  (wb_clk_sync_inGreyCount),
    .async_reset    (pciw_clear)
) ;

always@(posedge wb_clock_in or posedge pciw_clear)
begin
    if (pciw_clear)
        wb_clk_inGreyCount <= #`FF_DELAY 0 ;
    else
        wb_clk_inGreyCount <= # `FF_DELAY wb_clk_sync_inGreyCount ;
end

always@(posedge wb_clock_in or posedge pciw_clear)
begin
    if (pciw_clear)
    begin
        outGreyCount <= #`FF_DELAY 0 ;
    end
    else
    if (out_count_en)
        outGreyCount <= #`FF_DELAY outNextGreyCount ;
end

always@(posedge pci_clock_in or posedge pciw_clear)
begin
    if (pciw_clear)
        pciw_inTransactionCount <= #`FF_DELAY 1 ;
    else
    if (in_count_en)
        pciw_inTransactionCount <= #`FF_DELAY pciw_inTransactionCount + 1'b1 ;
end

always@(posedge wb_clock_in or posedge pciw_clear)
begin
    if (pciw_clear)
        pciw_outTransactionCount <= #`FF_DELAY 1 ;
    else
    if (out_count_en)
        pciw_outTransactionCount <= #`FF_DELAY pciw_outTransactionCount + 1'b1 ;
end

assign pciw_transaction_ready_out = wb_clk_inGreyCount != outGreyCount ;

assign pcir_transaction_ready_out  = 1'b0 ;

endmodule