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这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":114:42:114:47|Input port bit <1> of ta2_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":114:42:114:47|Input port bit <0> of ta2_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <19> of ta3_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <18> of ta3_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <17> of ta3_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <16> of ta3_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <15> of ta3_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <14> of ta3_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <13> of ta3_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <12> of ta3_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <11> of ta3_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <10> of ta3_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <9> of ta3_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <8> of ta3_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <7> of ta3_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <6> of ta3_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <5> of ta3_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <4> of ta3_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <3> of ta3_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <2> of ta3_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <1> of ta3_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <0> of ta3_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <19> of ta4_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <18> of ta4_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <17> of ta4_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <16> of ta4_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <15> of ta4_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <14> of ta4_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <13> of ta4_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <12> of ta4_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <11> of ta4_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <10> of ta4_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <9> of ta4_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <8> of ta4_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <7> of ta4_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <6> of ta4_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <5> of ta4_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <4> of ta4_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <3> of ta4_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <2> of ta4_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <1> of ta4_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <0> of ta4_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <19> of ta5_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <18> of ta5_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <17> of ta5_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <16> of ta5_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <15> of ta5_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <14> of ta5_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <13> of ta5_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <12> of ta5_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <11> of ta5_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <10> of ta5_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <9> of ta5_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <8> of ta5_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <7> of ta5_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <6> of ta5_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <5> of ta5_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <4> of ta5_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <3> of ta5_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <2> of ta5_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <1> of ta5_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <0> of ta5_in[19:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":118:13:118:20|Input port bit <5> of at_en_in[5:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":118:13:118:20|Input port bit <4> of at_en_in[5:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":118:13:118:20|Input port bit <3> of at_en_in[5:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":118:13:118:20|Input port bit <2> of at_en_in[5:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":118:13:118:20|Input port bit <0> of at_en_in[5:0] is unused

@W: CL159 :"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":100:42:100:48|Input bar0_in is unused
@W: CL159 :"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":102:42:102:48|Input bar2_in is unused
@W: CL159 :"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":103:42:103:48|Input bar3_in is unused
@W: CL159 :"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":104:42:104:48|Input bar4_in is unused
@W: CL159 :"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":105:42:105:48|Input bar5_in is unused
@W: CL159 :"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":106:42:106:47|Input am0_in is unused
@W: CL159 :"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":108:42:108:47|Input am2_in is unused
@W: CL159 :"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":109:42:109:47|Input am3_in is unused
@W: CL159 :"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":110:42:110:47|Input am4_in is unused
@W: CL159 :"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":111:42:111:47|Input am5_in is unused
@W: CL159 :"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":112:42:112:47|Input ta0_in is unused
@W: CL159 :"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":114:42:114:47|Input ta2_in is unused
@W: CL159 :"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input ta3_in is unused
@W: CL159 :"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input ta4_in is unused
@W: CL159 :"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input ta5_in is unused
Synthesizing module pci_synchronizer_flop
	width=32'b00000000000000000000000000000001
	reset_val=32'b00000000000000000000000000000000
   Generated name = pci_synchronizer_flop_1_0
Synthesizing module pci_delayed_sync
Synthesizing module pci_delayed_write_reg
Synthesizing module pci_master32_sm_if
@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_master32_sm_if.v":192:16:192:34|Input port bit <3> of wbw_fifo_control_in[3:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_master32_sm_if.v":192:16:192:34|Input port bit <2> of wbw_fifo_control_in[3:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_master32_sm_if.v":192:16:192:34|Input port bit <1> of wbw_fifo_control_in[3:0] is unused

Synthesizing module pci_frame_crit
Synthesizing module pci_frame_load_crit
Synthesizing module pci_irdy_out_crit
Synthesizing module pci_mas_ad_load_crit
Synthesizing module pci_mas_ch_state_crit
Synthesizing module pci_mas_ad_en_crit
Synthesizing module pci_cbe_en_crit
Synthesizing module pci_frame_en_crit
Synthesizing module pci_master32_sm
@N: CL201 :"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_master32_sm.v":245:0:245:5|Trying to extract state machine for register cur_state
Extracted state machine for register cur_state
State machine has 4 reachable states with original encodings of:
   0001
   0010
   0100
   1000
Synthesizing module pci_wb_slave_unit
@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_slave_unit.v":200:16:200:25|Input port bit <0> of wbu_map_in[5:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_slave_unit.v":201:16:201:29|Input port bit <0> of wbu_pref_en_in[5:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_slave_unit.v":202:16:202:28|Input port bit <0> of wbu_mrl_en_in[5:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_slave_unit.v":230:16:230:31|Input port bit <23> of wbu_ccyc_addr_in[23:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_slave_unit.v":230:16:230:31|Input port bit <22> of wbu_ccyc_addr_in[23:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_slave_unit.v":230:16:230:31|Input port bit <21> of wbu_ccyc_addr_in[23:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_slave_unit.v":230:16:230:31|Input port bit <20> of wbu_ccyc_addr_in[23:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_slave_unit.v":230:16:230:31|Input port bit <19> of wbu_ccyc_addr_in[23:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_slave_unit.v":230:16:230:31|Input port bit <18> of wbu_ccyc_addr_in[23:0] is unused

@W:"E:\lizhen\PCI_Bridge\PCI_Bridge_Guest_UART\pci_wb_slave_unit.v":230:16:230:31|Input port bit <17> of wbu_ccyc_addr_in[23