wbs_uart.v

这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序

module wbs_uart(
	// Clock and reset
	wb_clk_i, wb_rst_i,

	// WISHBONE Slave I/F
	wbs_cyc_i, wbs_stb_i, wbs_sel_i, wbs_we_i,
	wbs_adr_i, wbs_dat_i, wbs_cti_i,wbs_bte_i,
	wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
	//UART serial input/output
     srx_pad_i,
     stx_pad_o


);
 
// Clock and reset
//
input			wb_clk_i;	// Wishbone Clock
input			wb_rst_i;	// Reset

//
// WISHBONE Slave I/F
//
input			wbs_cyc_i;
input			wbs_stb_i;
input	[3:0]	wbs_sel_i;
input			wbs_we_i;
input	[31:0]	wbs_adr_i;
input	[31:0]	wbs_dat_i;
input			wbs_cti_i,wbs_bte_i;
output	[31:0]	wbs_dat_o;
output			wbs_ack_o;
output			wbs_err_o;
output			wbs_rty_o;

 //UART serial input/output
 input  srx_pad_i;
 output stx_pad_o;

  wire   [4:0]	 addr;
  wire    int_o;
  
  
  wire   rts_pad_o; 
  wire   cts_pad_i;
  wire   dtr_pad_o;
  wire   dsr_pad_i;
  wire   ri_pad_i;
  wire   dcd_pad_i;	
  
  reg  [1:0] low_addr;	 
 
   
  assign  addr[4:2] = wbs_adr_i[4:2];
  assign  addr[1:0]	= low_addr[1:0];
   
  assign wbs_rty_o = 1'b0;
  assign wbs_err_o = 1'b0;

 
always @(wbs_sel_i)
begin
  case (wbs_sel_i)
	    4'b0001: low_addr[1:0] = 2'b00;
	    4'b0010: low_addr[1:0] = 2'b01;
	    4'b0100: low_addr[1:0] = 2'b10;
	    4'b1000: low_addr[1:0] = 2'b11;
		default:  low_addr[1:0] = 2'b00; 
	endcase 

end



uart_top  uart_top_exp(
// Wishbone signals
   .wb_clk_i(wb_clk_i),
   .wb_rst_i(wb_rst_i),
   .wb_adr_i(addr),
   .wb_dat_i(wbs_dat_i),
   .wb_dat_o(wbs_dat_o),
   .wb_we_i(wbs_we_i),
   .wb_stb_i(wbs_stb_i),
   .wb_cyc_i(wbs_cyc_i),
   .wb_ack_o(wbs_ack_o),
   .wb_sel_i(wbs_sel_i),
   .int_o(int_o), // interrupt request
   // serial input/output
   .stx_pad_o(stx_pad_o),
   .srx_pad_i(srx_pad_i),
   // modem signals
   .rts_pad_o(rts_pad_o),
   .cts_pad_i(cts_pad_i),
   .dtr_pad_o(dtr_pad_o),
   .dsr_pad_i(dsr_pad_i),
   .ri_pad_i(ri_pad_i),
   .dcd_pad_i(dcd_pad_i)

);


endmodule