wb_master.srd

这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序

f "noname"; #file 0
f "d:\program files\synplicity\synplify_76\bin\..\lib\xilinx\unisim.v"; #file 1
f "f:\lizheng\fiberoptical\fpga\pci_bridge_guest_uart\wb_master.v"; #file 2
VNAME 'work.WB_Master.verilog'; # view id 0
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