📄 pci_bridge32.v
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.pciu_err_bc_out (pciu_err_bc_out), .pciu_err_data_out (pciu_err_data_out), .pciu_err_be_out (pciu_err_be_out), .pciu_err_signal_out (pciu_err_signal_out), .pciu_err_source_out (pciu_err_source_out), .pciu_err_rty_exp_out (pciu_err_rty_exp_out), .pciu_conf_offset_out (pciu_conf_offset_out), .pciu_conf_renable_out (pciu_conf_renable_out), .pciu_conf_wenable_out (pciu_conf_wenable_out), .pciu_conf_be_out (pciu_conf_be_out), .pciu_conf_data_out (pciu_conf_data_out), .pciu_pci_drcomp_pending_out (pciu_pci_drcomp_pending_out), .pciu_pciw_fifo_empty_out (pciu_pciw_fifo_empty_out)`ifdef PCI_BIST , .mbist_si_i (mbist_so_o_internal), .mbist_so_o (mbist_so_o), .mbist_ctrl_i (mbist_ctrl_i)`endif);// CONFIGURATION SPACE INPUTS`ifdef HOST wire [11:0] conf_w_addr_in = wbu_conf_offset_out ; wire [31:0] conf_w_data_in = wbu_conf_data_out ; wire conf_w_we_in = wbu_conf_wenable_out ; wire conf_w_re_in = wbu_conf_renable_out ; wire [3:0] conf_w_be_in = wbu_conf_be_out ; wire conf_w_clock = wb_clk ; wire [11:0] conf_r_addr_in = pciu_conf_offset_out ; wire conf_r_re_in = pciu_conf_renable_out ;`else`ifdef GUEST wire [11:0] conf_r_addr_in = wbu_conf_offset_out ; wire conf_r_re_in = wbu_conf_renable_out ; wire conf_w_clock = pci_clk ; wire [11:0] conf_w_addr_in = pciu_conf_offset_out ; wire [31:0] conf_w_data_in = pciu_conf_data_out ; wire conf_w_we_in = pciu_conf_wenable_out ; wire conf_w_re_in = pciu_conf_renable_out ; wire [3:0] conf_w_be_in = pciu_conf_be_out ;`endif`endifwire conf_perr_in = parchk_par_err_detect_out ;wire conf_serr_in = parchk_sig_serr_out ;wire conf_master_abort_recv_in = wbu_mabort_rec_out ;wire conf_target_abort_recv_in = wbu_tabort_rec_out ;wire conf_target_abort_set_in = pciu_pciif_tabort_set_out ;wire conf_master_data_par_err_in = parchk_perr_mas_detect_out ;wire [3:0] conf_pci_err_be_in = pciu_err_be_out ;wire [3:0] conf_pci_err_bc_in = pciu_err_bc_out;wire conf_pci_err_es_in = pciu_err_source_out ;wire conf_pci_err_rty_exp_in = pciu_err_rty_exp_out ;wire conf_pci_err_sig_in = pciu_err_signal_out ;wire [31:0] conf_pci_err_addr_in = pciu_err_addr_out ;wire [31:0] conf_pci_err_data_in = pciu_err_data_out ;wire [3:0] conf_wb_err_be_in = out_bckp_cbe_out ;wire [3:0] conf_wb_err_bc_in = wbu_err_bc_out ;wire conf_wb_err_rty_exp_in = wbu_err_rty_exp_out ;wire conf_wb_err_es_in = wbu_err_source_out ;wire conf_wb_err_sig_in = wbu_err_signal_out ;wire [31:0] conf_wb_err_addr_in = wbu_err_addr_out ;wire [31:0] conf_wb_err_data_in = out_bckp_ad_out ;wire conf_isr_int_prop_in = pci_into_conf_isr_int_prop_out ;wire conf_par_err_int_in = parchk_perr_mas_detect_out ;wire conf_sys_err_int_in = parchk_sig_serr_out ;pci_conf_space configuration( .reset (reset), .pci_clk (pci_clk), .wb_clk (wb_clk), .w_conf_address_in (conf_w_addr_in), .w_conf_data_in (conf_w_data_in), .w_conf_data_out (conf_w_data_out), .r_conf_address_in (conf_r_addr_in), .r_conf_data_out (conf_r_data_out), .w_we_i (conf_w_we_in), .w_re (conf_w_re_in), .r_re (conf_r_re_in), .w_byte_en_in (conf_w_be_in), .w_clock (conf_w_clock), .serr_enable (conf_serr_enable_out), .perr_response (conf_perr_response_out), .pci_master_enable (conf_pci_master_enable_out), .memory_space_enable (conf_mem_space_enable_out), .io_space_enable (conf_io_space_enable_out), .perr_in (conf_perr_in), .serr_in (conf_serr_in), .master_abort_recv (conf_master_abort_recv_in), .target_abort_recv (conf_target_abort_recv_in), .target_abort_set (conf_target_abort_set_in), .master_data_par_err (conf_master_data_par_err_in), .cache_line_size_to_pci (conf_cache_line_size_to_pci_out), .cache_line_size_to_wb (conf_cache_line_size_to_wb_out), .cache_lsize_not_zero_to_wb (conf_cache_lsize_not_zero_to_wb_out), .latency_tim (conf_latency_tim_out), .pci_base_addr0 (conf_pci_ba0_out), .pci_base_addr1 (conf_pci_ba1_out), .pci_base_addr2 (conf_pci_ba2_out), .pci_base_addr3 (conf_pci_ba3_out), .pci_base_addr4 (conf_pci_ba4_out), .pci_base_addr5 (conf_pci_ba5_out), .pci_memory_io0 (conf_pci_mem_io0_out), .pci_memory_io1 (conf_pci_mem_io1_out), .pci_memory_io2 (conf_pci_mem_io2_out), .pci_memory_io3 (conf_pci_mem_io3_out), .pci_memory_io4 (conf_pci_mem_io4_out), .pci_memory_io5 (conf_pci_mem_io5_out), .pci_addr_mask0 (conf_pci_am0_out), .pci_addr_mask1 (conf_pci_am1_out), .pci_addr_mask2 (conf_pci_am2_out), .pci_addr_mask3 (conf_pci_am3_out), .pci_addr_mask4 (conf_pci_am4_out), .pci_addr_mask5 (conf_pci_am5_out), .pci_tran_addr0 (conf_pci_ta0_out), .pci_tran_addr1 (conf_pci_ta1_out), .pci_tran_addr2 (conf_pci_ta2_out), .pci_tran_addr3 (conf_pci_ta3_out), .pci_tran_addr4 (conf_pci_ta4_out), .pci_tran_addr5 (conf_pci_ta5_out), .pci_img_ctrl0 (conf_pci_img_ctrl0_out), .pci_img_ctrl1 (conf_pci_img_ctrl1_out), .pci_img_ctrl2 (conf_pci_img_ctrl2_out), .pci_img_ctrl3 (conf_pci_img_ctrl3_out), .pci_img_ctrl4 (conf_pci_img_ctrl4_out), .pci_img_ctrl5 (conf_pci_img_ctrl5_out), .pci_error_be (conf_pci_err_be_in), .pci_error_bc (conf_pci_err_bc_in), .pci_error_rty_exp (conf_pci_err_rty_exp_in), .pci_error_es (conf_pci_err_es_in), .pci_error_sig (conf_pci_err_sig_in), .pci_error_addr (conf_pci_err_addr_in), .pci_error_data (conf_pci_err_data_in), .wb_base_addr0 (conf_wb_ba0_out), .wb_base_addr1 (conf_wb_ba1_out), .wb_base_addr2 (conf_wb_ba2_out), .wb_base_addr3 (conf_wb_ba3_out), .wb_base_addr4 (conf_wb_ba4_out), .wb_base_addr5 (conf_wb_ba5_out), .wb_memory_io0 (conf_wb_mem_io0_out), .wb_memory_io1 (conf_wb_mem_io1_out), .wb_memory_io2 (conf_wb_mem_io2_out), .wb_memory_io3 (conf_wb_mem_io3_out), .wb_memory_io4 (conf_wb_mem_io4_out), .wb_memory_io5 (conf_wb_mem_io5_out), .wb_addr_mask0 (conf_wb_am0_out), .wb_addr_mask1 (conf_wb_am1_out), .wb_addr_mask2 (conf_wb_am2_out), .wb_addr_mask3 (conf_wb_am3_out), .wb_addr_mask4 (conf_wb_am4_out), .wb_addr_mask5 (conf_wb_am5_out), .wb_tran_addr0 (conf_wb_ta0_out), .wb_tran_addr1 (conf_wb_ta1_out), .wb_tran_addr2 (conf_wb_ta2_out), .wb_tran_addr3 (conf_wb_ta3_out), .wb_tran_addr4 (conf_wb_ta4_out), .wb_tran_addr5 (conf_wb_ta5_out), .wb_img_ctrl0 (conf_wb_img_ctrl0_out), .wb_img_ctrl1 (conf_wb_img_ctrl1_out), .wb_img_ctrl2 (conf_wb_img_ctrl2_out), .wb_img_ctrl3 (conf_wb_img_ctrl3_out), .wb_img_ctrl4 (conf_wb_img_ctrl4_out), .wb_img_ctrl5 (conf_wb_img_ctrl5_out), .wb_error_be (conf_wb_err_be_in), .wb_error_bc (conf_wb_err_bc_in), .wb_error_rty_exp (conf_wb_err_rty_exp_in), .wb_error_es (conf_wb_err_es_in), .wb_error_sig (conf_wb_err_sig_in), .wb_error_addr (conf_wb_err_addr_in), .wb_error_data (conf_wb_err_data_in), .config_addr (conf_ccyc_addr_out), .icr_soft_res (conf_soft_res_out), .int_out (conf_int_out), .isr_int_prop (conf_isr_int_prop_in), .isr_par_err_int (conf_par_err_int_in), .isr_sys_err_int (conf_sys_err_int_in), .pci_init_complete_out (conf_pci_init_complete_out), .wb_init_complete_out (conf_wb_init_complete_out) `ifdef PCI_CPCI_HS_IMPLEMENT , .pci_cpci_hs_enum_oe_o (pci_cpci_hs_enum_oe_o) , .pci_cpci_hs_led_oe_o (pci_cpci_hs_led_oe_o ) , .pci_cpci_hs_es_i (pci_cpci_hs_es_i) `endif `ifdef PCI_SPOCI , // Serial power on configuration interface .spoci_scl_oe_o (spoci_scl_oe_o ) , .spoci_sda_i (spoci_sda_i ) , .spoci_sda_oe_o (spoci_sda_oe_o ) `endif ) ;// pci data io multiplexer inputswire pci_mux_tar_ad_en_in = pciu_pciif_ad_en_out ;wire pci_mux_tar_ad_en_reg_in = out_bckp_tar_ad_en_out ;wire [31:0] pci_mux_tar_ad_in = pciu_pciif_ad_out ;wire pci_mux_devsel_in = pciu_pciif_devsel_out ;wire pci_mux_devsel_en_in = pciu_pciif_devsel_en_out ;wire pci_mux_trdy_in = pciu_pciif_trdy_out ;wire pci_mux_trdy_en_in = pciu_pciif_trdy_en_out ;wire pci_mux_stop_in = pciu_pciif_stop_out ;wire pci_mux_stop_en_in = pciu_pciif_stop_en_out ;wire pci_mux_tar_load_in = pciu_ad_load_out ;wire pci_mux_tar_load_on_transfer_in = pciu_ad_load_on_transfer_out ;wire pci_mux_mas_ad_en_in = wbu_pciif_ad_en_out ;wire [31:0] pci_mux_mas_ad_in = wbu_pciif_ad_out ;wire pci_mux_frame_in = wbu_pciif_frame_out ;wire pci_mux_frame_en_in = wbu_pciif_frame_en_out ;wire pci_mux_irdy_in = wbu_pciif_irdy_out;wire pci_mux_irdy_en_in = wbu_pciif_irdy_en_out;wire pci_mux_mas_load_in = wbu_ad_load_out ;wire pci_mux_mas_load_on_transfer_in = wbu_ad_load_on_transfer_out ;wire [3:0] pci_mux_cbe_in = wbu_pciif_cbe_out ;wire pci_mux_cbe_en_in = wbu_pciif_cbe_en_out ;wire pci_mux_par_in = parchk_pci_par_out ;wire pci_mux_par_en_in = parchk_pci_par_en_out ;wire pci_mux_perr_in = parchk_pci_perr_out ;wire pci_mux_perr_en_in = parchk_pci_perr_en_out ;wire pci_mux_serr_in = parchk_pci_serr_out ;wire pci_mux_serr_en_in = parchk_pci_serr_en_out;wire pci_mux_req_in = wbu_pciif_req_out ;wire pci_mux_frame_load_in = wbu_pciif_frame_load_out ;wire pci_mux_pci_irdy_in = pci_irdy_i ;wire pci_mux_pci_trdy_in = pci_trdy_i ;wire pci_mux_pci_frame_in = pci_frame_i ;wire pci_mux_pci_stop_in = pci_stop_i ;wire pci_mux_init_complete_in = conf_pci_init_complete_out ;pci_io_mux pci_io_mux( .reset_in (reset), .clk_in (pci_clk), .frame_in (pci_mux_frame_in), .frame_en_in (pci_mux_frame_en_in), .frame_load_in (pci_mux_frame_load_in), .irdy_in (pci_mux_irdy_in), .irdy_en_in (pci_mux_irdy_en_in), .devsel_in (pci_mux_devsel_in), .devsel_en_in (pci_mux_devsel_en_in), .trdy_in (pci_mux_trdy_in), .trdy_en_in (pci_mux_trdy_en_in), .stop_in (pci_mux_stop_in), .stop_en_in (pci_mux_stop_en_in), .master_load_in (pci_mux_mas_load_in), .master_load_on_transfer_in (pci_mux_mas_load_on_transfer_in), .target_load_in (pci_mux_tar_load_in), .target_load_on_transfer_in (pci_mux_tar_load_on_transfer_in), .cbe_in (pci_mux_cbe_in), .cbe_en_in (pci_mux_cbe_en_in), .mas_ad_in (pci_mux_mas_ad_in), .tar_ad_in (pci_mux_tar_ad_in), .mas_ad_en_in (pci_mux_mas_ad_en_in), .tar_ad_en_in (pci_mux_tar_ad_en_in), .tar_ad_en_reg_in (pci_mux_tar_ad_en_reg_in), .par_in (pci_mux_par_in), .par_en_in (pci_mux_par_en_in), .perr_in (pci_mux_perr_in), .perr_en_in (pci_mux_perr_en_in), .serr_in (pci_mux_serr_in), .serr_en_in (pci_mux_serr_en_in), .frame_en_out (pci_mux_fra
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