pci_bridge32.v

这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序

output          wbm_stb_o ;
output          wbm_we_o ;
output  [2:0]   wbm_cti_o ;
output  [1:0]   wbm_bte_o ;
input           wbm_ack_i ;
input           wbm_rty_i ;
input           wbm_err_i ;

// pci interface - system pins
input   pci_clk_i ;
input   pci_rst_i ;
output  pci_rst_o ;
output  pci_rst_oe_o ;

input   pci_inta_i ;
output  pci_inta_o ;
output  pci_inta_oe_o ;

// arbitration pins
output  pci_req_o ;
output  pci_req_oe_o ;

input   pci_gnt_i ;

// protocol pins
input   pci_frame_i ;
output  pci_frame_o ;
output  pci_frame_oe_o ;
output  pci_irdy_oe_o ;
output  pci_devsel_oe_o ;
output  pci_trdy_oe_o ;
output  pci_stop_oe_o ;
output  [31:0] pci_ad_oe_o ;
output  [3:0]  pci_cbe_oe_o ;

input   pci_irdy_i ;
output  pci_irdy_o ;

input   pci_idsel_i ;

input   pci_devsel_i ;
output  pci_devsel_o ;

input   pci_trdy_i ;
output  pci_trdy_o ;

input   pci_stop_i ;
output  pci_stop_o ;

// data transfer pins
input   [31:0]  pci_ad_i ;
output  [31:0]  pci_ad_o ;

input   [3:0]   pci_cbe_i ;
output  [3:0]   pci_cbe_o ;

// parity generation and checking pins
input   pci_par_i ;
output  pci_par_o ;
output  pci_par_oe_o ;

input   pci_perr_i ;
output  pci_perr_o ;
output  pci_perr_oe_o ;

// system error pin
output  pci_serr_o ;
output  pci_serr_oe_o ;

`ifdef PCI_BIST
/*-----------------------------------------------------
BIST debug chain port signals
-----------------------------------------------------*/
input   mbist_si_i;       // bist scan serial in
output  mbist_so_o;       // bist scan serial out
input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
`endif

`ifdef PCI_CPCI_HS_IMPLEMENT
    // Compact PCI Hot Swap signals
output  pci_cpci_hs_enum_o      ;   //  ENUM# output with output enable (open drain)
output  pci_cpci_hs_enum_oe_o   ;   //  ENUM# enum output enable
output  pci_cpci_hs_led_o       ;   //  LED output with output enable (open drain)
output  pci_cpci_hs_led_oe_o    ;   //  LED output enable
input   pci_cpci_hs_es_i        ;   //  ejector switch state indicator input

assign  pci_cpci_hs_enum_o = 1'b0   ;
assign  pci_cpci_hs_led_o  = 1'b0   ;
`endif

`ifdef PCI_SPOCI
output  spoci_scl_o     ;
output  spoci_scl_oe_o  ;
input   spoci_sda_i     ;
output  spoci_sda_o     ;
output  spoci_sda_oe_o  ;

assign  spoci_scl_o = 1'b0  ;
assign  spoci_sda_o = 1'b0  ;
`endif

// declare clock and reset wires
wire pci_clk = pci_clk_i ;
wire wb_clk  = wb_clk_i ;
wire reset ; // assigned at pci bridge reset and interrupt logic

/*=========================================================================================================
First comes definition of all modules' outputs, so they can be assigned to any other module's input later
  in the file, when module is instantiated
=========================================================================================================*/
// PCI BRIDGE RESET AND INTERRUPT LOGIC OUTPUTS
wire    pci_reso_reset ;
wire    pci_reso_pci_rstn_out ;
wire    pci_reso_pci_rstn_en_out ;
wire    pci_reso_rst_o ;
wire    pci_into_pci_intan_out ;
wire    pci_into_pci_intan_en_out ;
wire    pci_into_int_o ;
wire    pci_into_conf_isr_int_prop_out ;

// assign pci bridge reset interrupt logic outputs to top outputs where possible
assign reset            = pci_reso_reset ;
assign pci_rst_o     = pci_reso_pci_rstn_out ;
assign pci_rst_oe_o  = pci_reso_pci_rstn_en_out ;
assign wb_rst_o         = pci_reso_rst_o ;
assign pci_inta_o    = pci_into_pci_intan_out ;
assign pci_inta_oe_o = pci_into_pci_intan_en_out ;
assign wb_int_o         = pci_into_int_o ;

// WISHBONE SLAVE UNIT OUTPUTS
wire    [31:0]  wbu_sdata_out ;
wire            wbu_ack_out ;
wire            wbu_rty_out ;
wire            wbu_err_out ;
wire            wbu_pciif_req_out ;
wire            wbu_pciif_frame_out ;
wire            wbu_pciif_frame_en_out ;
wire            wbu_pciif_irdy_out ;
wire            wbu_pciif_irdy_en_out ;
wire    [31:0]  wbu_pciif_ad_out ;
wire            wbu_pciif_ad_en_out ;
wire    [3:0]   wbu_pciif_cbe_out ;
wire            wbu_pciif_cbe_en_out ;
wire    [31:0]  wbu_err_addr_out ;
wire    [3:0]   wbu_err_bc_out ;
wire            wbu_err_signal_out ;
wire            wbu_err_source_out ;
wire            wbu_err_rty_exp_out ;
wire            wbu_tabort_rec_out ;
wire            wbu_mabort_rec_out ;
wire    [11:0]  wbu_conf_offset_out ;
wire            wbu_conf_renable_out ;
wire            wbu_conf_wenable_out ;
wire    [3:0]   wbu_conf_be_out ;
wire    [31:0]  wbu_conf_data_out ;
wire            wbu_del_read_comp_pending_out ;
wire            wbu_wbw_fifo_empty_out ;
wire            wbu_ad_load_out ;
wire            wbu_ad_load_on_transfer_out ;
wire            wbu_pciif_frame_load_out ;

// PCI TARGET UNIT OUTPUTS
wire    [31:0]  pciu_adr_out ;
wire    [31:0]  pciu_mdata_out ;
wire            pciu_cyc_out ;
wire            pciu_stb_out ;
wire            pciu_we_out ;
wire    [2:0]   pciu_cti_out ;
wire    [1:0]   pciu_bte_out ;
wire    [3:0]   pciu_sel_out ;
wire            pciu_pciif_trdy_out ;
wire            pciu_pciif_stop_out ;
wire            pciu_pciif_devsel_out ;
wire            pciu_pciif_trdy_en_out ;
wire            pciu_pciif_stop_en_out ;
wire            pciu_pciif_devsel_en_out ;
wire            pciu_ad_load_out ;
wire            pciu_ad_load_on_transfer_out ;
wire   [31:0]   pciu_pciif_ad_out ;
wire            pciu_pciif_ad_en_out ;
wire            pciu_pciif_tabort_set_out ;
wire    [31:0]  pciu_err_addr_out ;
wire    [3:0]   pciu_err_bc_out ;
wire    [31:0]  pciu_err_data_out ;
wire    [3:0]   pciu_err_be_out ;
wire            pciu_err_signal_out ;
wire            pciu_err_source_out ;
wire            pciu_err_rty_exp_out ;
wire    [11:0]  pciu_conf_offset_out ;
wire            pciu_conf_renable_out ;
wire            pciu_conf_wenable_out ;
wire    [3:0]   pciu_conf_be_out ;
wire    [31:0]  pciu_conf_data_out ;
wire            pciu_pci_drcomp_pending_out ;
wire            pciu_pciw_fifo_empty_out ;

// assign pci target unit's outputs to top outputs where possible
assign wbm_adr_o    =   pciu_adr_out ;
assign wbm_dat_o    =   pciu_mdata_out ;
assign wbm_cyc_o    =   pciu_cyc_out ;
assign wbm_stb_o    =   pciu_stb_out ;
assign wbm_we_o     =   pciu_we_out ;
assign wbm_cti_o    =   pciu_cti_out ;
assign wbm_bte_o    =   pciu_bte_out ;
assign wbm_sel_o    =   pciu_sel_out ;

// CONFIGURATION SPACE OUTPUTS
wire    [31:0]  conf_w_data_out ;
wire    [31:0]  conf_r_data_out ;
wire            conf_serr_enable_out ;
wire            conf_perr_response_out ;
wire            conf_pci_master_enable_out ;
wire            conf_mem_space_enable_out ;
wire            conf_io_space_enable_out ;
wire    [7:0]   conf_cache_line_size_to_pci_out ;
wire    [7:0]   conf_cache_line_size_to_wb_out ;
wire            conf_cache_lsize_not_zero_to_wb_out ;
wire    [7:0]   conf_latency_tim_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ba0_out ;
wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ba1_out ;
wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ba2_out ;
wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ba3_out ;
wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ba4_out ;
wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ba5_out ;
wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ta0_out ;
wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ta1_out ;
wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ta2_out ;
wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ta3_out ;
wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ta4_out ;
wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ta5_out ;
wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_am0_out ;
wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_am1_out ;
wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_am2_out ;
wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_am3_out ;
wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_am4_out ;
wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_am5_out ;

wire            conf_pci_mem_io0_out ;
wire            conf_pci_mem_io1_out ;
wire            conf_pci_mem_io2_out ;
wire            conf_pci_mem_io3_out ;
wire            conf_pci_mem_io4_out ;
wire            conf_pci_mem_io5_out ;

wire    [1:0]   conf_pci_img_ctrl0_out ;
wire    [1:0]   conf_pci_img_ctrl1_out ;
wire    [1:0]   conf_pci_img_ctrl2_out ;
wire    [1:0]   conf_pci_img_ctrl3_out ;
wire    [1:0]   conf_pci_img_ctrl4_out ;
wire    [1:0]   conf_pci_img_ctrl5_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ba0_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ba1_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ba2_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ba3_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ba4_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ba5_out ;

wire            conf_wb_mem_io0_out ;
wire            conf_wb_mem_io1_out ;
wire            conf_wb_mem_io2_out ;
wire            conf_wb_mem_io3_out ;
wire            conf_wb_mem_io4_out ;
wire            conf_wb_mem_io5_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_am0_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_am1_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_am2_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_am3_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_am4_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_am5_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ta0_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ta1_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ta2_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ta3_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ta4_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ta5_out ;
wire    [2:0]   conf_wb_img_ctrl0_out ;
wire    [2:0]   conf_wb_img_ctrl1_out ;
wire    [2:0]   conf_wb_img_ctrl2_out ;
wire    [2:0]   conf_wb_img_ctrl3_out ;
wire    [2:0]   conf_wb_img_ctrl4_out ;
wire    [2:0]   conf_wb_img_ctrl5_out ;
wire    [23:0]  conf_ccyc_addr_out ;
wire            conf_soft_res_out ;
wire            conf_int_out ;